u-boot/arch
Simon Glass 37c664e825 x86: Make sure the SPL image ends on a suitable boundary
The part of U-Boot that actually ends up in u-boot-nodtb.bin is not built
with any particular alignment. It ends at the start of the BSS section.
The BSS section selects its own alignment, which may larger.
This means that there can be a gap of a few bytes between the image
ending and BSS starting.

Since u-boot.bin is build by joining u-boot-nodtb.bin and u-boot.dtb (with
perhaps some padding for BSS), the expected result is not obtained. U-Boot
uses the end of BSS to find the devicetree, so this means that it cannot
be found.

Add 32-byte alignment of BSS so that the image size is correct and
appending the devicetree will place it at the end of BSS.

Example SPL output without this patch:

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .text         000142a1  fef40000  fef40000  00001000  2**4
                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
  1 .u_boot_list  000014a4  fef542a8  fef542a8  000152a8  2**3
                  CONTENTS, ALLOC, LOAD, RELOC, DATA
  2 .rodata       0000599c  fef55760  fef55760  00016760  2**5
                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
  3 .data         00000970  fef5b100  fef5b100  0001c100  2**5
                  CONTENTS, ALLOC, LOAD, RELOC, DATA
  4 .binman_sym_table 00000020  fef5ba70  fef5ba70  0001ca70  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  5 .bss          00000060  fef5baa0  fef5baa0  00000000  2**5
                  ALLOC

You can see that .bss is aligned to 2**5 (32 bytes). This is because of
the mallinfo struct in dlmalloc.c:

 17 .bss.current_mallinfo 00000028  00000000  00000000  000004c0  2**5
                  ALLOC

In this case the size of u-boot-spl-nodtb.bin is 0x1ba90. This matches up
with the _image_binary_end symbol:

fef5ba90 g       .binman_sym_table      00000000 _image_binary_end

But BSS starts 16 bytes later, at 0xfef5baa0, due to the 32-byte
alignment. So we must align _image_binary_end to a 32-byte boundary. This
forces the binary size to be 0x1baa0, i.e. ending at the start of bss, as
expected.

Note that gcc reports __BIGGEST_ALIGNMENT__ of 16 on this build, even
though it generates an object file with a member that requests 32-byte
alignment.

The current_mallinfo struct is 40 bytes in size. Increasing the struct to
68 bytes (i.e. just above a 64-byte boundary) does not cause the alignment
to go above 32 bytes. So it seems that 32 bytes is the maximum alignment
at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add more details in the commit message to help people understand]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-02-01 15:29:02 +08:00
..
arc Driver model: make some udevice fields private 2021-01-05 22:34:43 -05:00
arm Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh 2021-01-31 14:23:47 -05:00
m68k common: board_r: Drop arch-specific ifdefs around initr_trap 2021-01-15 14:36:12 -05:00
microblaze microblaze: Enable GCC garbage collector for full U-Boot 2020-11-20 10:42:53 +01:00
mips mips: mtmips: add two reference boards for mt7620 2021-01-24 21:39:26 +01:00
nds32 arc: m68k: nds32: nios2: sh: xtensa: Add empty spl.h header 2021-01-05 12:24:40 -07:00
nios2 arc: m68k: nds32: nios2: sh: xtensa: Add empty spl.h header 2021-01-05 12:24:40 -07:00
powerpc common: board_r: Drop arch-specific ifdefs around initr_trap 2021-01-15 14:36:12 -05:00
riscv riscv: dts: Add device tree for Microchip Icicle Kit 2021-01-18 11:06:38 +08:00
sandbox sandbox: keep time offset when resetting 2021-01-30 14:25:42 -07:00
sh arc: m68k: nds32: nios2: sh: xtensa: Add empty spl.h header 2021-01-05 12:24:40 -07:00
x86 x86: Make sure the SPL image ends on a suitable boundary 2021-02-01 15:29:02 +08:00
xtensa arc: m68k: nds32: nios2: sh: xtensa: Add empty spl.h header 2021-01-05 12:24:40 -07:00
.gitignore
Kconfig linker_lists: Fix alignment issue 2020-12-18 20:32:21 -07:00
u-boot-elf.lds arch: Add explicit linker script for u-boot-elf 2020-04-03 11:52:55 -04:00