mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-23 19:43:33 +00:00
6fa41cdd19
The device tree binding provides for getting VBUS state from a device referenced by phandle, as an optional alternative to using a GPIO. In U-Boot, where there is no power supply class, this VBUS detection will be implemented using a regulator device and its get_enable method. Let's hook this up to the PHY driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
665 lines
16 KiB
C
665 lines
16 KiB
C
/*
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* Allwinner sun4i USB PHY driver
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*
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* Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
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* Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
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* Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
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*
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* Modelled arch/arm/mach-sunxi/usb_phy.c to compatible with generic-phy.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <log.h>
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#include <dm/device.h>
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#include <generic-phy.h>
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#include <phy-sun4i-usb.h>
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#include <reset.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <power/regulator.h>
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#define REG_ISCR 0x00
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#define REG_PHYCTL_A10 0x04
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#define REG_PHYBIST 0x08
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#define REG_PHYTUNE 0x0c
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#define REG_PHYCTL_A33 0x10
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#define REG_PHY_OTGCTL 0x20
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#define REG_PMU_UNK1 0x10
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/* Common Control Bits for Both PHYs */
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#define PHY_PLL_BW 0x03
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#define PHY_RES45_CAL_EN 0x0c
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/* Private Control Bits for Each PHY */
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#define PHY_TX_AMPLITUDE_TUNE 0x20
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#define PHY_TX_SLEWRATE_TUNE 0x22
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#define PHY_DISCON_TH_SEL 0x2a
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#define PHY_SQUELCH_DETECT 0x3c
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#define PHYCTL_DATA BIT(7)
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#define OTGCTL_ROUTE_MUSB BIT(0)
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#define PHY_TX_RATE BIT(4)
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#define PHY_TX_MAGNITUDE BIT(2)
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#define PHY_TX_AMPLITUDE_LEN 5
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#define PHY_RES45_CAL_DATA BIT(0)
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#define PHY_RES45_CAL_LEN 1
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#define PHY_DISCON_TH_LEN 2
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#define SUNXI_AHB_ICHR8_EN BIT(10)
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#define SUNXI_AHB_INCR4_BURST_EN BIT(9)
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#define SUNXI_AHB_INCRX_ALIGN_EN BIT(8)
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#define SUNXI_ULPI_BYPASS_EN BIT(0)
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/* A83T specific control bits for PHY0 */
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#define PHY_CTL_VBUSVLDEXT BIT(5)
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#define PHY_CTL_SIDDQ BIT(3)
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/* A83T specific control bits for PHY2 HSIC */
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#define SUNXI_EHCI_HS_FORCE BIT(20)
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#define SUNXI_HSIC_CONNECT_INT BIT(16)
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#define SUNXI_HSIC BIT(1)
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#define MAX_PHYS 4
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enum sun4i_usb_phy_type {
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sun4i_a10_phy,
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sun6i_a31_phy,
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sun8i_a33_phy,
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sun8i_a83t_phy,
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sun8i_h3_phy,
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sun8i_r40_phy,
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sun8i_v3s_phy,
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sun50i_a64_phy,
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sun50i_h6_phy,
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};
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struct sun4i_usb_phy_cfg {
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int num_phys;
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enum sun4i_usb_phy_type type;
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u32 disc_thresh;
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u8 phyctl_offset;
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bool dedicated_clocks;
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bool enable_pmu_unk1;
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bool phy0_dual_route;
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int missing_phys;
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};
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struct sun4i_usb_phy_info {
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const char *gpio_vbus;
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const char *gpio_vbus_det;
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const char *gpio_id_det;
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} phy_info[] = {
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{
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.gpio_vbus = CONFIG_USB0_VBUS_PIN,
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.gpio_vbus_det = CONFIG_USB0_VBUS_DET,
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.gpio_id_det = CONFIG_USB0_ID_DET,
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},
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{
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.gpio_vbus = CONFIG_USB1_VBUS_PIN,
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.gpio_vbus_det = NULL,
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.gpio_id_det = NULL,
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},
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{
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.gpio_vbus = CONFIG_USB2_VBUS_PIN,
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.gpio_vbus_det = NULL,
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.gpio_id_det = NULL,
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},
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{
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.gpio_vbus = CONFIG_USB3_VBUS_PIN,
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.gpio_vbus_det = NULL,
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.gpio_id_det = NULL,
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},
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};
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struct sun4i_usb_phy_plat {
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void __iomem *pmu;
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int power_on_count;
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int gpio_vbus;
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int gpio_vbus_det;
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int gpio_id_det;
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struct clk clocks;
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struct reset_ctl resets;
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int id;
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};
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struct sun4i_usb_phy_data {
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void __iomem *base;
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const struct sun4i_usb_phy_cfg *cfg;
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struct sun4i_usb_phy_plat *usb_phy;
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struct udevice *vbus_power_supply;
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};
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static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
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static void sun4i_usb_phy_write(struct phy *phy, u32 addr, u32 data, int len)
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{
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struct sun4i_usb_phy_data *phy_data = dev_get_priv(phy->dev);
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struct sun4i_usb_phy_plat *usb_phy = &phy_data->usb_phy[phy->id];
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u32 temp, usbc_bit = BIT(usb_phy->id * 2);
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void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
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int i;
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if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
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/* SoCs newer than A33 need us to set phyctl to 0 explicitly */
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writel(0, phyctl);
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}
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for (i = 0; i < len; i++) {
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temp = readl(phyctl);
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/* clear the address portion */
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temp &= ~(0xff << 8);
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/* set the address */
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temp |= ((addr + i) << 8);
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writel(temp, phyctl);
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/* set the data bit and clear usbc bit*/
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temp = readb(phyctl);
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if (data & 0x1)
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temp |= PHYCTL_DATA;
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else
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temp &= ~PHYCTL_DATA;
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temp &= ~usbc_bit;
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writeb(temp, phyctl);
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/* pulse usbc_bit */
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temp = readb(phyctl);
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temp |= usbc_bit;
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writeb(temp, phyctl);
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temp = readb(phyctl);
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temp &= ~usbc_bit;
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writeb(temp, phyctl);
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data >>= 1;
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}
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}
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static void sun4i_usb_phy_passby(struct phy *phy, bool enable)
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{
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struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
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struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
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u32 bits, reg_value;
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if (!usb_phy->pmu)
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return;
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bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
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SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
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/* A83T USB2 is HSIC */
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if (data->cfg->type == sun8i_a83t_phy && usb_phy->id == 2)
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bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
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SUNXI_HSIC;
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reg_value = readl(usb_phy->pmu);
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if (enable)
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reg_value |= bits;
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else
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reg_value &= ~bits;
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writel(reg_value, usb_phy->pmu);
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}
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static int sun4i_usb_phy_power_on(struct phy *phy)
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{
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struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
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struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
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if (initial_usb_scan_delay) {
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mdelay(initial_usb_scan_delay);
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initial_usb_scan_delay = 0;
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}
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usb_phy->power_on_count++;
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if (usb_phy->power_on_count != 1)
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return 0;
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if (usb_phy->gpio_vbus >= 0)
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gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP);
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return 0;
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}
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static int sun4i_usb_phy_power_off(struct phy *phy)
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{
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struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
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struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
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usb_phy->power_on_count--;
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if (usb_phy->power_on_count != 0)
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return 0;
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if (usb_phy->gpio_vbus >= 0)
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gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE);
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return 0;
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}
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static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, bool id_det)
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{
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u32 regval;
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regval = readl(data->base + REG_PHY_OTGCTL);
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if (!id_det) {
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/* Host mode. Route phy0 to EHCI/OHCI */
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regval &= ~OTGCTL_ROUTE_MUSB;
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} else {
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/* Peripheral mode. Route phy0 to MUSB */
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regval |= OTGCTL_ROUTE_MUSB;
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}
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writel(regval, data->base + REG_PHY_OTGCTL);
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}
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static int sun4i_usb_phy_init(struct phy *phy)
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{
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struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
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struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
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u32 val;
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int ret;
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ret = clk_enable(&usb_phy->clocks);
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if (ret) {
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dev_err(phy->dev, "failed to enable usb_%ldphy clock\n",
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phy->id);
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return ret;
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}
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ret = reset_deassert(&usb_phy->resets);
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if (ret) {
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dev_err(phy->dev, "failed to deassert usb_%ldreset reset\n",
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phy->id);
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return ret;
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}
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if (data->cfg->type == sun8i_a83t_phy ||
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data->cfg->type == sun50i_h6_phy) {
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if (phy->id == 0) {
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val = readl(data->base + data->cfg->phyctl_offset);
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val |= PHY_CTL_VBUSVLDEXT;
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val &= ~PHY_CTL_SIDDQ;
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writel(val, data->base + data->cfg->phyctl_offset);
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}
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} else {
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if (usb_phy->pmu && data->cfg->enable_pmu_unk1) {
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val = readl(usb_phy->pmu + REG_PMU_UNK1);
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writel(val & ~2, usb_phy->pmu + REG_PMU_UNK1);
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}
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if (usb_phy->id == 0)
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sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
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PHY_RES45_CAL_DATA,
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PHY_RES45_CAL_LEN);
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/* Adjust PHY's magnitude and rate */
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sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE,
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PHY_TX_MAGNITUDE | PHY_TX_RATE,
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PHY_TX_AMPLITUDE_LEN);
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/* Disconnect threshold adjustment */
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sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
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data->cfg->disc_thresh, PHY_DISCON_TH_LEN);
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}
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#ifdef CONFIG_USB_MUSB_SUNXI
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/* Needed for HCI and conflicts with MUSB, keep PHY0 on MUSB */
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if (usb_phy->id != 0)
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sun4i_usb_phy_passby(phy, true);
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/* Route PHY0 to MUSB to allow USB gadget */
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if (data->cfg->phy0_dual_route)
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sun4i_usb_phy0_reroute(data, true);
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#else
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sun4i_usb_phy_passby(phy, true);
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/* Route PHY0 to HCI to allow USB host */
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if (data->cfg->phy0_dual_route)
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sun4i_usb_phy0_reroute(data, false);
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#endif
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return 0;
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}
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static int sun4i_usb_phy_exit(struct phy *phy)
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{
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struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
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struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
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int ret;
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if (phy->id == 0) {
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if (data->cfg->type == sun8i_a83t_phy ||
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data->cfg->type == sun50i_h6_phy) {
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void __iomem *phyctl = data->base +
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data->cfg->phyctl_offset;
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writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
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}
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}
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sun4i_usb_phy_passby(phy, false);
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ret = clk_disable(&usb_phy->clocks);
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if (ret) {
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dev_err(phy->dev, "failed to disable usb_%ldphy clock\n",
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phy->id);
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return ret;
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}
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ret = reset_assert(&usb_phy->resets);
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if (ret) {
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dev_err(phy->dev, "failed to assert usb_%ldreset reset\n",
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phy->id);
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return ret;
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}
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return 0;
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}
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static int sun4i_usb_phy_xlate(struct phy *phy,
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struct ofnode_phandle_args *args)
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{
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struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
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if (args->args_count >= data->cfg->num_phys)
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return -EINVAL;
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if (data->cfg->missing_phys & BIT(args->args[0]))
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return -ENODEV;
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if (args->args_count)
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phy->id = args->args[0];
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else
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phy->id = 0;
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debug("%s: phy_id = %ld\n", __func__, phy->id);
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return 0;
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}
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int sun4i_usb_phy_vbus_detect(struct phy *phy)
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{
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struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
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struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
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int err = 1, retries = 3;
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if (usb_phy->gpio_vbus_det >= 0) {
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err = gpio_get_value(usb_phy->gpio_vbus_det);
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/*
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* Vbus may have been provided by the board and just turned off
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* some milliseconds ago on reset. What we're measuring then is
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* a residual charge on Vbus. Sleep a bit and try again.
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*/
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while (err > 0 && retries--) {
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mdelay(100);
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err = gpio_get_value(usb_phy->gpio_vbus_det);
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}
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} else if (data->vbus_power_supply) {
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err = regulator_get_enable(data->vbus_power_supply);
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}
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return err;
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}
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int sun4i_usb_phy_id_detect(struct phy *phy)
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{
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struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
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struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
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if (usb_phy->gpio_id_det < 0)
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return usb_phy->gpio_id_det;
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return gpio_get_value(usb_phy->gpio_id_det);
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}
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void sun4i_usb_phy_set_squelch_detect(struct phy *phy, bool enabled)
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{
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sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
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}
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static struct phy_ops sun4i_usb_phy_ops = {
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.of_xlate = sun4i_usb_phy_xlate,
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.init = sun4i_usb_phy_init,
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.power_on = sun4i_usb_phy_power_on,
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.power_off = sun4i_usb_phy_power_off,
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.exit = sun4i_usb_phy_exit,
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};
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static int sun4i_usb_phy_probe(struct udevice *dev)
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{
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struct sun4i_usb_phy_plat *plat = dev_get_plat(dev);
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struct sun4i_usb_phy_data *data = dev_get_priv(dev);
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int i, ret;
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data->cfg = (const struct sun4i_usb_phy_cfg *)dev_get_driver_data(dev);
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if (!data->cfg)
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return -EINVAL;
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data->base = (void __iomem *)devfdt_get_addr_name(dev, "phy_ctrl");
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if (IS_ERR(data->base))
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return PTR_ERR(data->base);
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device_get_supply_regulator(dev, "usb0_vbus_power-supply",
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&data->vbus_power_supply);
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data->usb_phy = plat;
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for (i = 0; i < data->cfg->num_phys; i++) {
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struct sun4i_usb_phy_plat *phy = &plat[i];
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struct sun4i_usb_phy_info *info = &phy_info[i];
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char name[16];
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if (data->cfg->missing_phys & BIT(i))
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continue;
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phy->gpio_vbus = sunxi_name_to_gpio(info->gpio_vbus);
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if (phy->gpio_vbus >= 0) {
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ret = gpio_request(phy->gpio_vbus, "usb_vbus");
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if (ret)
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return ret;
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ret = gpio_direction_output(phy->gpio_vbus, 0);
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if (ret)
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return ret;
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}
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phy->gpio_vbus_det = sunxi_name_to_gpio(info->gpio_vbus_det);
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|
if (phy->gpio_vbus_det >= 0) {
|
|
ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
|
|
if (ret)
|
|
return ret;
|
|
ret = gpio_direction_input(phy->gpio_vbus_det);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
phy->gpio_id_det = sunxi_name_to_gpio(info->gpio_id_det);
|
|
if (phy->gpio_id_det >= 0) {
|
|
ret = gpio_request(phy->gpio_id_det, "usb_id_det");
|
|
if (ret)
|
|
return ret;
|
|
ret = gpio_direction_input(phy->gpio_id_det);
|
|
if (ret)
|
|
return ret;
|
|
sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
|
|
}
|
|
|
|
if (data->cfg->dedicated_clocks)
|
|
snprintf(name, sizeof(name), "usb%d_phy", i);
|
|
else
|
|
strlcpy(name, "usb_phy", sizeof(name));
|
|
|
|
ret = clk_get_by_name(dev, name, &phy->clocks);
|
|
if (ret) {
|
|
dev_err(dev, "failed to get usb%d_phy clock phandle\n", i);
|
|
return ret;
|
|
}
|
|
|
|
snprintf(name, sizeof(name), "usb%d_reset", i);
|
|
ret = reset_get_by_name(dev, name, &phy->resets);
|
|
if (ret) {
|
|
dev_err(dev, "failed to get usb%d_reset reset phandle\n", i);
|
|
return ret;
|
|
}
|
|
|
|
if (i || data->cfg->phy0_dual_route) {
|
|
snprintf(name, sizeof(name), "pmu%d", i);
|
|
phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);
|
|
if (IS_ERR(phy->pmu))
|
|
return PTR_ERR(phy->pmu);
|
|
}
|
|
|
|
phy->id = i;
|
|
};
|
|
|
|
debug("Allwinner Sun4I USB PHY driver loaded\n");
|
|
return 0;
|
|
}
|
|
|
|
static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
|
|
.num_phys = 3,
|
|
.type = sun4i_a10_phy,
|
|
.disc_thresh = 3,
|
|
.phyctl_offset = REG_PHYCTL_A10,
|
|
.dedicated_clocks = false,
|
|
.enable_pmu_unk1 = false,
|
|
};
|
|
|
|
static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
|
|
.num_phys = 2,
|
|
.type = sun4i_a10_phy,
|
|
.disc_thresh = 2,
|
|
.phyctl_offset = REG_PHYCTL_A10,
|
|
.dedicated_clocks = false,
|
|
.enable_pmu_unk1 = false,
|
|
};
|
|
|
|
static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
|
|
.num_phys = 3,
|
|
.type = sun6i_a31_phy,
|
|
.disc_thresh = 3,
|
|
.phyctl_offset = REG_PHYCTL_A10,
|
|
.dedicated_clocks = true,
|
|
.enable_pmu_unk1 = false,
|
|
};
|
|
|
|
static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
|
|
.num_phys = 3,
|
|
.type = sun4i_a10_phy,
|
|
.disc_thresh = 2,
|
|
.phyctl_offset = REG_PHYCTL_A10,
|
|
.dedicated_clocks = false,
|
|
.enable_pmu_unk1 = false,
|
|
};
|
|
|
|
static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
|
|
.num_phys = 2,
|
|
.type = sun4i_a10_phy,
|
|
.disc_thresh = 3,
|
|
.phyctl_offset = REG_PHYCTL_A10,
|
|
.dedicated_clocks = true,
|
|
.enable_pmu_unk1 = false,
|
|
};
|
|
|
|
static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
|
|
.num_phys = 2,
|
|
.type = sun8i_a33_phy,
|
|
.disc_thresh = 3,
|
|
.phyctl_offset = REG_PHYCTL_A33,
|
|
.dedicated_clocks = true,
|
|
.enable_pmu_unk1 = false,
|
|
};
|
|
|
|
static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
|
|
.num_phys = 3,
|
|
.type = sun8i_a83t_phy,
|
|
.phyctl_offset = REG_PHYCTL_A33,
|
|
.dedicated_clocks = true,
|
|
};
|
|
|
|
static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
|
|
.num_phys = 4,
|
|
.type = sun8i_h3_phy,
|
|
.disc_thresh = 3,
|
|
.phyctl_offset = REG_PHYCTL_A33,
|
|
.dedicated_clocks = true,
|
|
.enable_pmu_unk1 = true,
|
|
.phy0_dual_route = true,
|
|
};
|
|
|
|
static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
|
|
.num_phys = 3,
|
|
.type = sun8i_r40_phy,
|
|
.disc_thresh = 3,
|
|
.phyctl_offset = REG_PHYCTL_A33,
|
|
.dedicated_clocks = true,
|
|
.enable_pmu_unk1 = true,
|
|
.phy0_dual_route = true,
|
|
};
|
|
|
|
static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
|
|
.num_phys = 1,
|
|
.type = sun8i_v3s_phy,
|
|
.disc_thresh = 3,
|
|
.phyctl_offset = REG_PHYCTL_A33,
|
|
.dedicated_clocks = true,
|
|
.enable_pmu_unk1 = true,
|
|
.phy0_dual_route = true,
|
|
};
|
|
|
|
static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
|
|
.num_phys = 2,
|
|
.type = sun50i_a64_phy,
|
|
.disc_thresh = 3,
|
|
.phyctl_offset = REG_PHYCTL_A33,
|
|
.dedicated_clocks = true,
|
|
.enable_pmu_unk1 = true,
|
|
.phy0_dual_route = true,
|
|
};
|
|
|
|
static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
|
|
.num_phys = 4,
|
|
.type = sun50i_h6_phy,
|
|
.disc_thresh = 3,
|
|
.phyctl_offset = REG_PHYCTL_A33,
|
|
.dedicated_clocks = true,
|
|
.enable_pmu_unk1 = true,
|
|
.phy0_dual_route = true,
|
|
.missing_phys = BIT(1) | BIT(2),
|
|
};
|
|
|
|
static const struct udevice_id sun4i_usb_phy_ids[] = {
|
|
{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = (ulong)&sun4i_a10_cfg },
|
|
{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg },
|
|
{ .compatible = "allwinner,sun6i-a31-usb-phy", .data = (ulong)&sun6i_a31_cfg },
|
|
{ .compatible = "allwinner,sun7i-a20-usb-phy", .data = (ulong)&sun7i_a20_cfg },
|
|
{ .compatible = "allwinner,sun8i-a23-usb-phy", .data = (ulong)&sun8i_a23_cfg },
|
|
{ .compatible = "allwinner,sun8i-a33-usb-phy", .data = (ulong)&sun8i_a33_cfg },
|
|
{ .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
|
|
{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
|
|
{ .compatible = "allwinner,sun8i-r40-usb-phy", .data = (ulong)&sun8i_r40_cfg },
|
|
{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },
|
|
{ .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
|
|
{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = (ulong)&sun50i_h6_cfg},
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(sun4i_usb_phy) = {
|
|
.name = "sun4i_usb_phy",
|
|
.id = UCLASS_PHY,
|
|
.of_match = sun4i_usb_phy_ids,
|
|
.ops = &sun4i_usb_phy_ops,
|
|
.probe = sun4i_usb_phy_probe,
|
|
.plat_auto = sizeof(struct sun4i_usb_phy_plat[MAX_PHYS]),
|
|
.priv_auto = sizeof(struct sun4i_usb_phy_data),
|
|
};
|