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95ab5784bf
It is common to set all base address bits to one and all limit address bits to zero for disabling address forwarding. Forwarding is disabled when base address is higher than limit address, so this change should not have any effect. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
423 lines
12 KiB
C
423 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* PCI autoconfiguration library
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*
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* Author: Matt Porter <mporter@mvista.com>
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*
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* Copyright 2000 MontaVista Software Inc.
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <pci.h>
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#include "pci_internal.h"
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/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
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#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
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#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
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#endif
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static void dm_pciauto_setup_device(struct udevice *dev,
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struct pci_region *mem,
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struct pci_region *prefetch,
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struct pci_region *io)
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{
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u32 bar_response;
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pci_size_t bar_size;
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u16 cmdstat = 0;
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int bar, bar_nr = 0;
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int bars_num;
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u8 header_type;
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int rom_addr;
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pci_addr_t bar_value;
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struct pci_region *bar_res = NULL;
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int found_mem64 = 0;
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u16 class;
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dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
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cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
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PCI_COMMAND_MASTER;
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dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
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header_type &= 0x7f;
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switch (header_type) {
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case PCI_HEADER_TYPE_NORMAL:
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bars_num = 6;
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break;
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case PCI_HEADER_TYPE_BRIDGE:
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bars_num = 2;
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break;
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case PCI_HEADER_TYPE_CARDBUS:
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/* CardBus header does not have any BAR */
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bars_num = 0;
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break;
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default:
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/* Skip configuring BARs for unknown header types */
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bars_num = 0;
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break;
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}
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for (bar = PCI_BASE_ADDRESS_0;
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bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
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int ret = 0;
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/* Tickle the BAR and get the response */
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dm_pci_write_config32(dev, bar, 0xffffffff);
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dm_pci_read_config32(dev, bar, &bar_response);
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/* If BAR is not implemented (or invalid) go to the next BAR */
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if (!bar_response || bar_response == 0xffffffff)
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continue;
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found_mem64 = 0;
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/* Check the BAR type and set our address mask */
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if (bar_response & PCI_BASE_ADDRESS_SPACE) {
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bar_size = bar_response & PCI_BASE_ADDRESS_IO_MASK;
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bar_size &= ~(bar_size - 1);
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bar_res = io;
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debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
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bar_nr, (unsigned long long)bar_size);
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} else {
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if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
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PCI_BASE_ADDRESS_MEM_TYPE_64) {
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u32 bar_response_upper;
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u64 bar64;
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dm_pci_write_config32(dev, bar + 4, 0xffffffff);
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dm_pci_read_config32(dev, bar + 4,
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&bar_response_upper);
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bar64 = ((u64)bar_response_upper << 32) |
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bar_response;
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bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK)
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+ 1;
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found_mem64 = 1;
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} else {
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bar_size = (u32)(~(bar_response &
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PCI_BASE_ADDRESS_MEM_MASK) + 1);
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}
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if (prefetch &&
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(bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
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bar_res = prefetch;
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else
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bar_res = mem;
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debug("PCI Autoconfig: BAR %d, %s%s, size=0x%llx, ",
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bar_nr, bar_res == prefetch ? "Prf" : "Mem",
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found_mem64 ? "64" : "",
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(unsigned long long)bar_size);
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}
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ret = pciauto_region_allocate(bar_res, bar_size,
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&bar_value, found_mem64);
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if (ret)
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printf("PCI: Failed autoconfig bar %x\n", bar);
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if (!ret) {
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/* Write it out and update our limit */
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dm_pci_write_config32(dev, bar, (u32)bar_value);
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if (found_mem64) {
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bar += 4;
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#ifdef CONFIG_SYS_PCI_64BIT
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dm_pci_write_config32(dev, bar,
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(u32)(bar_value >> 32));
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#else
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/*
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* If we are a 64-bit decoder then increment to
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* the upper 32 bits of the bar and force it to
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* locate in the lower 4GB of memory.
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*/
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dm_pci_write_config32(dev, bar, 0x00000000);
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#endif
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}
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}
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cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
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PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
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debug("\n");
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bar_nr++;
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}
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/* Configure the expansion ROM address */
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if (header_type == PCI_HEADER_TYPE_NORMAL ||
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header_type == PCI_HEADER_TYPE_BRIDGE) {
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rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
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PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
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dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
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dm_pci_read_config32(dev, rom_addr, &bar_response);
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if (bar_response) {
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bar_size = -(bar_response & ~1);
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debug("PCI Autoconfig: ROM, size=%#x, ",
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(unsigned int)bar_size);
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if (pciauto_region_allocate(mem, bar_size, &bar_value,
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false) == 0) {
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dm_pci_write_config32(dev, rom_addr, bar_value);
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}
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cmdstat |= PCI_COMMAND_MEMORY;
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debug("\n");
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}
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}
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/* PCI_COMMAND_IO must be set for VGA device */
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dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
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if (class == PCI_CLASS_DISPLAY_VGA)
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cmdstat |= PCI_COMMAND_IO;
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dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
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dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
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CONFIG_SYS_PCI_CACHE_LINE_SIZE);
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dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
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}
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void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
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{
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struct pci_region *pci_mem;
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struct pci_region *pci_prefetch;
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struct pci_region *pci_io;
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u16 cmdstat, prefechable_64;
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u8 io_32;
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struct udevice *ctlr = pci_get_controller(dev);
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struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
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pci_mem = ctlr_hose->pci_mem;
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pci_prefetch = ctlr_hose->pci_prefetch;
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pci_io = ctlr_hose->pci_io;
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dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
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dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
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prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
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dm_pci_read_config8(dev, PCI_IO_BASE, &io_32);
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io_32 &= PCI_IO_RANGE_TYPE_MASK;
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/* Configure bus number registers */
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dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
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PCI_BUS(dm_pci_get_bdf(dev)) - dev_seq(ctlr));
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dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - dev_seq(ctlr));
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dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
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if (pci_mem) {
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/* Round memory allocator to 1MB boundary */
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pciauto_region_align(pci_mem, 0x100000);
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/*
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* Set up memory and I/O filter limits, assume 32-bit
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* I/O space
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*/
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dm_pci_write_config16(dev, PCI_MEMORY_BASE,
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((pci_mem->bus_lower & 0xfff00000) >> 16) &
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PCI_MEMORY_RANGE_MASK);
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cmdstat |= PCI_COMMAND_MEMORY;
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}
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if (pci_prefetch) {
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/* Round memory allocator to 1MB boundary */
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pciauto_region_align(pci_prefetch, 0x100000);
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/*
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* Set up memory and I/O filter limits, assume 32-bit
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* I/O space
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*/
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dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
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(((pci_prefetch->bus_lower & 0xfff00000) >> 16) &
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PCI_PREF_RANGE_MASK) | prefechable_64);
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if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
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#ifdef CONFIG_SYS_PCI_64BIT
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dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
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pci_prefetch->bus_lower >> 32);
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#else
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dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);
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#endif
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cmdstat |= PCI_COMMAND_MEMORY;
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} else {
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/* We don't support prefetchable memory for now, so disable */
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dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0xfff0 |
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prefechable_64);
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dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 |
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prefechable_64);
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if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
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dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
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dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
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}
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}
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if (pci_io) {
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/* Round I/O allocator to 4KB boundary */
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pciauto_region_align(pci_io, 0x1000);
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dm_pci_write_config8(dev, PCI_IO_BASE,
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(((pci_io->bus_lower & 0x0000f000) >> 8) &
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PCI_IO_RANGE_MASK) | io_32);
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if (io_32 == PCI_IO_RANGE_TYPE_32)
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dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
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(pci_io->bus_lower & 0xffff0000) >> 16);
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cmdstat |= PCI_COMMAND_IO;
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} else {
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/* Disable I/O if unsupported */
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dm_pci_write_config8(dev, PCI_IO_BASE, 0xf0 | io_32);
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dm_pci_write_config8(dev, PCI_IO_LIMIT, 0x0 | io_32);
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if (io_32 == PCI_IO_RANGE_TYPE_32) {
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dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, 0x0);
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dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 0x0);
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}
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}
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/* Enable memory and I/O accesses, enable bus master */
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dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
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}
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void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
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{
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struct pci_region *pci_mem;
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struct pci_region *pci_prefetch;
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struct pci_region *pci_io;
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struct udevice *ctlr = pci_get_controller(dev);
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struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
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pci_mem = ctlr_hose->pci_mem;
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pci_prefetch = ctlr_hose->pci_prefetch;
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pci_io = ctlr_hose->pci_io;
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/* Configure bus number registers */
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dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - dev_seq(ctlr));
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if (pci_mem) {
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/* Round memory allocator to 1MB boundary */
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pciauto_region_align(pci_mem, 0x100000);
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dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
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((pci_mem->bus_lower - 1) >> 16) &
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PCI_MEMORY_RANGE_MASK);
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}
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if (pci_prefetch) {
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u16 prefechable_64;
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dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,
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&prefechable_64);
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prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
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/* Round memory allocator to 1MB boundary */
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pciauto_region_align(pci_prefetch, 0x100000);
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dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
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(((pci_prefetch->bus_lower - 1) >> 16) &
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PCI_PREF_RANGE_MASK) | prefechable_64);
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if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
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#ifdef CONFIG_SYS_PCI_64BIT
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dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
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(pci_prefetch->bus_lower - 1) >> 32);
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#else
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dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
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#endif
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}
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if (pci_io) {
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u8 io_32;
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dm_pci_read_config8(dev, PCI_IO_LIMIT,
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&io_32);
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io_32 &= PCI_IO_RANGE_TYPE_MASK;
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/* Round I/O allocator to 4KB boundary */
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pciauto_region_align(pci_io, 0x1000);
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dm_pci_write_config8(dev, PCI_IO_LIMIT,
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((((pci_io->bus_lower - 1) & 0x0000f000) >> 8) &
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PCI_IO_RANGE_MASK) | io_32);
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if (io_32 == PCI_IO_RANGE_TYPE_32)
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dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
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((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
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}
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}
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/*
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* HJF: Changed this to return int. I think this is required
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* to get the correct result when scanning bridges
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*/
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int dm_pciauto_config_device(struct udevice *dev)
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{
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struct pci_region *pci_mem;
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struct pci_region *pci_prefetch;
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struct pci_region *pci_io;
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unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
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unsigned short class;
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struct udevice *ctlr = pci_get_controller(dev);
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struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
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int ret;
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pci_mem = ctlr_hose->pci_mem;
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pci_prefetch = ctlr_hose->pci_prefetch;
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pci_io = ctlr_hose->pci_io;
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dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
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switch (class) {
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case PCI_CLASS_BRIDGE_PCI:
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debug("PCI Autoconfig: Found P2P bridge, device %d\n",
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PCI_DEV(dm_pci_get_bdf(dev)));
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dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
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ret = dm_pci_hose_probe_bus(dev);
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if (ret < 0)
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return log_msg_ret("probe", ret);
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sub_bus = ret;
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break;
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case PCI_CLASS_BRIDGE_CARDBUS:
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/*
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* just do a minimal setup of the bridge,
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* let the OS take care of the rest
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*/
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dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
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debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
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PCI_DEV(dm_pci_get_bdf(dev)));
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break;
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#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
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case PCI_CLASS_BRIDGE_OTHER:
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debug("PCI Autoconfig: Skipping bridge device %d\n",
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PCI_DEV(dm_pci_get_bdf(dev)));
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break;
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#endif
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#if defined(CONFIG_ARCH_MPC834X)
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case PCI_CLASS_BRIDGE_OTHER:
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/*
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* The host/PCI bridge 1 seems broken in 8349 - it presents
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* itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
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* device claiming resources io/mem/irq.. we only allow for
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* the PIMMR window to be allocated (BAR0 - 1MB size)
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*/
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debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
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dm_pciauto_setup_device(dev, 0, hose->pci_mem,
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hose->pci_prefetch, hose->pci_io);
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break;
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#endif
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case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
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debug("PCI AutoConfig: Found PowerPC device\n");
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/* fall through */
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default:
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dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
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break;
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}
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return sub_bus;
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}
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