mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
379febac5a
The R40 is the successor to the A20. It is a hybrid of the A20, A33 and the H3. The R40's PIO controller is compatible with the A20, Reuse the A20 UART and I2C muxing code by adding the R40's macro. The display pipeline is the newer DE 2.0 variant. Block enabling video on R40 for now. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
756 lines
20 KiB
Text
756 lines
20 KiB
Text
if ARCH_SUNXI
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config IDENT_STRING
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default " Allwinner Technology"
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# FIXME: Should not redefine these Kconfig symbols
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config PRE_CONSOLE_BUFFER
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default y
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config SPL_GPIO_SUPPORT
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default y
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config SPL_LIBCOMMON_SUPPORT
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default y
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config SPL_LIBDISK_SUPPORT
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default y
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config SPL_LIBGENERIC_SUPPORT
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default y
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config SPL_MMC_SUPPORT
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depends on SPL && GENERIC_MMC
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default y
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config SPL_POWER_SUPPORT
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default y
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config SPL_SERIAL_SUPPORT
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default y
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config SUNXI_HIGH_SRAM
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bool
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default n
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---help---
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Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
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with the first SRAM region being located at address 0.
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Some newer SoCs map the boot ROM at address 0 instead and move the
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SRAM to 64KB, just behind the mask ROM.
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Chips using the latter setup are supposed to select this option to
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adjust the addresses accordingly.
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# Note only one of these may be selected at a time! But hidden choices are
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# not supported by Kconfig
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config SUNXI_GEN_SUN4I
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bool
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---help---
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Select this for sunxi SoCs which have resets and clocks set up
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as the original A10 (mach-sun4i).
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config SUNXI_GEN_SUN6I
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bool
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---help---
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Select this for sunxi SoCs which have sun6i like periphery, like
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separate ahb reset control registers, custom pmic bus, new style
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watchdog, etc.
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config MACH_SUNXI_H3_H5
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bool
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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choice
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prompt "Sunxi SoC Variant"
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optional
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config MACH_SUN4I
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bool "sun4i (Allwinner A10)"
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select CPU_V7
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select ARM_CORTEX_CPU_IS_UP
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select SUNXI_GEN_SUN4I
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select SUPPORT_SPL
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config MACH_SUN5I
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bool "sun5i (Allwinner A13)"
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select CPU_V7
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select ARM_CORTEX_CPU_IS_UP
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select SUNXI_GEN_SUN4I
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select SUPPORT_SPL
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config MACH_SUN6I
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bool "sun6i (Allwinner A31)"
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select CPU_V7
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ARCH_SUPPORT_PSCI
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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config MACH_SUN7I
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bool "sun7i (Allwinner A20)"
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select CPU_V7
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ARCH_SUPPORT_PSCI
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select SUNXI_GEN_SUN4I
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select SUPPORT_SPL
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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config MACH_SUN8I_A23
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bool "sun8i (Allwinner A23)"
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select CPU_V7
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ARCH_SUPPORT_PSCI
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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config MACH_SUN8I_A33
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bool "sun8i (Allwinner A33)"
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select CPU_V7
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ARCH_SUPPORT_PSCI
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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config MACH_SUN8I_A83T
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bool "sun8i (Allwinner A83T)"
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select CPU_V7
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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config MACH_SUN8I_H3
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bool "sun8i (Allwinner H3)"
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select CPU_V7
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ARCH_SUPPORT_PSCI
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select MACH_SUNXI_H3_H5
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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config MACH_SUN8I_R40
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bool "sun8i (Allwinner R40)"
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select CPU_V7
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select SUNXI_GEN_SUN6I
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config MACH_SUN9I
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bool "sun9i (Allwinner A80)"
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select CPU_V7
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select SUNXI_HIGH_SRAM
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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config MACH_SUN50I
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bool "sun50i (Allwinner A64)"
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select ARM64
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select SUNXI_GEN_SUN6I
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select SUNXI_HIGH_SRAM
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select SUPPORT_SPL
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config MACH_SUN50I_H5
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bool "sun50i (Allwinner H5)"
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select ARM64
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select MACH_SUNXI_H3_H5
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select SUNXI_HIGH_SRAM
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endchoice
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# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
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config MACH_SUN8I
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bool
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default y if MACH_SUN8I_A23
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default y if MACH_SUN8I_A33
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default y if MACH_SUN8I_A83T
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default y if MACH_SUNXI_H3_H5
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default y if MACH_SUN8I_R40
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config RESERVE_ALLWINNER_BOOT0_HEADER
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bool "reserve space for Allwinner boot0 header"
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select ENABLE_ARM_SOC_BOOT0_HOOK
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---help---
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Prepend a 1536 byte (empty) header to the U-Boot image file, to be
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filled with magic values post build. The Allwinner provided boot0
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blob relies on this information to load and execute U-Boot.
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Only needed on 64-bit Allwinner boards so far when using boot0.
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config ARM_BOOT_HOOK_RMR
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bool
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depends on ARM64
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default y
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select ENABLE_ARM_SOC_BOOT0_HOOK
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---help---
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Insert some ARM32 code at the very beginning of the U-Boot binary
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which uses an RMR register write to bring the core into AArch64 mode.
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The very first instruction acts as a switch, since it's carefully
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chosen to be a NOP in one mode and a branch in the other, so the
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code would only be executed if not already in AArch64.
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This allows both the SPL and the U-Boot proper to be entered in
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either mode and switch to AArch64 if needed.
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config DRAM_TYPE
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int "sunxi dram type"
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depends on MACH_SUN8I_A83T
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default 3
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---help---
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Set the dram type, 3: DDR3, 7: LPDDR3
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config DRAM_CLK
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int "sunxi dram clock speed"
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default 792 if MACH_SUN9I
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default 312 if MACH_SUN6I || MACH_SUN8I
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default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
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default 672 if MACH_SUN50I
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---help---
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Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
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must be a multiple of 24. For the sun9i (A80), the tested values
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(for DDR3-1600) are 312 to 792.
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if MACH_SUN5I || MACH_SUN7I
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config DRAM_MBUS_CLK
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int "sunxi mbus clock speed"
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default 300
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---help---
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Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
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endif
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config DRAM_ZQ
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int "sunxi dram zq value"
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default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
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default 127 if MACH_SUN7I
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default 4145117 if MACH_SUN9I
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default 3881915 if MACH_SUN50I
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---help---
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Set the dram zq value.
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config DRAM_ODT_EN
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bool "sunxi dram odt enable"
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default n if !MACH_SUN8I_A23
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default y if MACH_SUN8I_A23
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default y if MACH_SUN50I
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---help---
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Select this to enable dram odt (on die termination).
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if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
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config DRAM_EMR1
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int "sunxi dram emr1 value"
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default 0 if MACH_SUN4I
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default 4 if MACH_SUN5I || MACH_SUN7I
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---help---
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Set the dram controller emr1 value.
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config DRAM_TPR3
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hex "sunxi dram tpr3 value"
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default 0
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---help---
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Set the dram controller tpr3 parameter. This parameter configures
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the delay on the command lane and also phase shifts, which are
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applied for sampling incoming read data. The default value 0
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means that no phase/delay adjustments are necessary. Properly
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configuring this parameter increases reliability at high DRAM
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clock speeds.
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config DRAM_DQS_GATING_DELAY
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hex "sunxi dram dqs_gating_delay value"
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default 0
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---help---
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Set the dram controller dqs_gating_delay parmeter. Each byte
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encodes the DQS gating delay for each byte lane. The delay
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granularity is 1/4 cycle. For example, the value 0x05060606
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means that the delay is 5 quarter-cycles for one lane (1.25
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cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
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The default value 0 means autodetection. The results of hardware
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autodetection are not very reliable and depend on the chip
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temperature (sometimes producing different results on cold start
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and warm reboot). But the accuracy of hardware autodetection
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is usually good enough, unless running at really high DRAM
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clocks speeds (up to 600MHz). If unsure, keep as 0.
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choice
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prompt "sunxi dram timings"
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default DRAM_TIMINGS_VENDOR_MAGIC
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---help---
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Select the timings of the DDR3 chips.
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config DRAM_TIMINGS_VENDOR_MAGIC
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bool "Magic vendor timings from Android"
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---help---
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The same DRAM timings as in the Allwinner boot0 bootloader.
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config DRAM_TIMINGS_DDR3_1066F_1333H
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bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
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---help---
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Use the timings of the standard JEDEC DDR3-1066F speed bin for
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DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
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for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
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used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
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or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
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that down binning to DDR3-1066F is supported (because DDR3-1066F
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uses a bit faster timings than DDR3-1333H).
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config DRAM_TIMINGS_DDR3_800E_1066G_1333J
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bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
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---help---
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Use the timings of the slowest possible JEDEC speed bin for the
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selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
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DDR3-800E, DDR3-1066G or DDR3-1333J.
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endchoice
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endif
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if MACH_SUN8I_A23
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config DRAM_ODT_CORRECTION
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int "sunxi dram odt correction value"
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default 0
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---help---
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Set the dram odt correction value (range -255 - 255). In allwinner
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fex files, this option is found in bits 8-15 of the u32 odt_en variable
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in the [dram] section. When bit 31 of the odt_en variable is set
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then the correction is negative. Usually the value for this is 0.
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endif
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config SYS_CLK_FREQ
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default 1008000000 if MACH_SUN4I
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default 1008000000 if MACH_SUN5I
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default 1008000000 if MACH_SUN6I
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default 912000000 if MACH_SUN7I
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default 1008000000 if MACH_SUN8I
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default 1008000000 if MACH_SUN9I
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default 816000000 if MACH_SUN50I
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config SYS_CONFIG_NAME
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default "sun4i" if MACH_SUN4I
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default "sun5i" if MACH_SUN5I
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default "sun6i" if MACH_SUN6I
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default "sun7i" if MACH_SUN7I
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default "sun8i" if MACH_SUN8I
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default "sun9i" if MACH_SUN9I
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default "sun50i" if MACH_SUN50I
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config SYS_BOARD
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default "sunxi"
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config SYS_SOC
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default "sunxi"
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config UART0_PORT_F
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bool "UART0 on MicroSD breakout board"
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default n
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---help---
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Repurpose the SD card slot for getting access to the UART0 serial
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console. Primarily useful only for low level u-boot debugging on
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tablets, where normal UART0 is difficult to access and requires
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device disassembly and/or soldering. As the SD card can't be used
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at the same time, the system can be only booted in the FEL mode.
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Only enable this if you really know what you are doing.
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config OLD_SUNXI_KERNEL_COMPAT
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bool "Enable workarounds for booting old kernels"
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default n
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---help---
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Set this to enable various workarounds for old kernels, this results in
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sub-optimal settings for newer kernels, only enable if needed.
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config MACPWR
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string "MAC power pin"
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default ""
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help
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Set the pin used to power the MAC. This takes a string in the format
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understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
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config MMC0_CD_PIN
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string "Card detect pin for mmc0"
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default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
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default ""
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---help---
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Set the card detect pin for mmc0, leave empty to not use cd. This
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takes a string in the format understood by sunxi_name_to_gpio, e.g.
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PH1 for pin 1 of port H.
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config MMC1_CD_PIN
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string "Card detect pin for mmc1"
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default ""
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---help---
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See MMC0_CD_PIN help text.
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config MMC2_CD_PIN
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string "Card detect pin for mmc2"
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default ""
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---help---
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See MMC0_CD_PIN help text.
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config MMC3_CD_PIN
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string "Card detect pin for mmc3"
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default ""
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---help---
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See MMC0_CD_PIN help text.
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config MMC1_PINS
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string "Pins for mmc1"
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default ""
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---help---
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Set the pins used for mmc1, when applicable. This takes a string in the
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format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
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config MMC2_PINS
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string "Pins for mmc2"
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default ""
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---help---
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See MMC1_PINS help text.
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config MMC3_PINS
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string "Pins for mmc3"
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default ""
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---help---
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See MMC1_PINS help text.
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config MMC_SUNXI_SLOT_EXTRA
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int "mmc extra slot number"
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default -1
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---help---
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sunxi builds always enable mmc0, some boards also have a second sdcard
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slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
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support for this.
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config INITIAL_USB_SCAN_DELAY
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int "delay initial usb scan by x ms to allow builtin devices to init"
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default 0
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---help---
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Some boards have on board usb devices which need longer than the
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USB spec's 1 second to connect from board powerup. Set this config
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option to a non 0 value to add an extra delay before the first usb
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bus scan.
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config USB0_VBUS_PIN
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string "Vbus enable pin for usb0 (otg)"
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default ""
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---help---
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Set the Vbus enable pin for usb0 (otg). This takes a string in the
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format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
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config USB0_VBUS_DET
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string "Vbus detect pin for usb0 (otg)"
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default ""
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---help---
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Set the Vbus detect pin for usb0 (otg). This takes a string in the
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format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
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config USB0_ID_DET
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string "ID detect pin for usb0 (otg)"
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default ""
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---help---
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Set the ID detect pin for usb0 (otg). This takes a string in the
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format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
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config USB1_VBUS_PIN
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string "Vbus enable pin for usb1 (ehci0)"
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default "PH6" if MACH_SUN4I || MACH_SUN7I
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default "PH27" if MACH_SUN6I
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---help---
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Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
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a string in the format understood by sunxi_name_to_gpio, e.g.
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PH1 for pin 1 of port H.
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config USB2_VBUS_PIN
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string "Vbus enable pin for usb2 (ehci1)"
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default "PH3" if MACH_SUN4I || MACH_SUN7I
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default "PH24" if MACH_SUN6I
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---help---
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See USB1_VBUS_PIN help text.
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config USB3_VBUS_PIN
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string "Vbus enable pin for usb3 (ehci2)"
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default ""
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---help---
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See USB1_VBUS_PIN help text.
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config I2C0_ENABLE
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bool "Enable I2C/TWI controller 0"
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default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
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default n if MACH_SUN6I || MACH_SUN8I
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select CMD_I2C
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---help---
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This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
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its clock and setting up the bus. This is especially useful on devices
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with slaves connected to the bus or with pins exposed through e.g. an
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expansion port/header.
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config I2C1_ENABLE
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bool "Enable I2C/TWI controller 1"
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default n
|
|
select CMD_I2C
|
|
---help---
|
|
See I2C0_ENABLE help text.
|
|
|
|
config I2C2_ENABLE
|
|
bool "Enable I2C/TWI controller 2"
|
|
default n
|
|
select CMD_I2C
|
|
---help---
|
|
See I2C0_ENABLE help text.
|
|
|
|
if MACH_SUN6I || MACH_SUN7I
|
|
config I2C3_ENABLE
|
|
bool "Enable I2C/TWI controller 3"
|
|
default n
|
|
select CMD_I2C
|
|
---help---
|
|
See I2C0_ENABLE help text.
|
|
endif
|
|
|
|
if SUNXI_GEN_SUN6I
|
|
config R_I2C_ENABLE
|
|
bool "Enable the PRCM I2C/TWI controller"
|
|
# This is used for the pmic on H3
|
|
default y if SY8106A_POWER
|
|
select CMD_I2C
|
|
---help---
|
|
Set this to y to enable the I2C controller which is part of the PRCM.
|
|
endif
|
|
|
|
if MACH_SUN7I
|
|
config I2C4_ENABLE
|
|
bool "Enable I2C/TWI controller 4"
|
|
default n
|
|
select CMD_I2C
|
|
---help---
|
|
See I2C0_ENABLE help text.
|
|
endif
|
|
|
|
config AXP_GPIO
|
|
bool "Enable support for gpio-s on axp PMICs"
|
|
default n
|
|
---help---
|
|
Say Y here to enable support for the gpio pins of the axp PMIC ICs.
|
|
|
|
config VIDEO
|
|
bool "Enable graphical uboot console on HDMI, LCD or VGA"
|
|
depends on !MACH_SUN8I_A83T
|
|
depends on !MACH_SUNXI_H3_H5
|
|
depends on !MACH_SUN8I_R40
|
|
depends on !MACH_SUN9I
|
|
depends on !MACH_SUN50I
|
|
default y
|
|
---help---
|
|
Say Y here to add support for using a cfb console on the HDMI, LCD
|
|
or VGA output found on most sunxi devices. See doc/README.video for
|
|
info on how to select the video output and mode.
|
|
|
|
config VIDEO_HDMI
|
|
bool "HDMI output support"
|
|
depends on VIDEO && !MACH_SUN8I
|
|
default y
|
|
---help---
|
|
Say Y here to add support for outputting video over HDMI.
|
|
|
|
config VIDEO_VGA
|
|
bool "VGA output support"
|
|
depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
|
|
default n
|
|
---help---
|
|
Say Y here to add support for outputting video over VGA.
|
|
|
|
config VIDEO_VGA_VIA_LCD
|
|
bool "VGA via LCD controller support"
|
|
depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
|
|
default n
|
|
---help---
|
|
Say Y here to add support for external DACs connected to the parallel
|
|
LCD interface driving a VGA connector, such as found on the
|
|
Olimex A13 boards.
|
|
|
|
config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
|
|
bool "Force sync active high for VGA via LCD controller support"
|
|
depends on VIDEO_VGA_VIA_LCD
|
|
default n
|
|
---help---
|
|
Say Y here if you've a board which uses opendrain drivers for the vga
|
|
hsync and vsync signals. Opendrain drivers cannot generate steep enough
|
|
positive edges for a stable video output, so on boards with opendrain
|
|
drivers the sync signals must always be active high.
|
|
|
|
config VIDEO_VGA_EXTERNAL_DAC_EN
|
|
string "LCD panel power enable pin"
|
|
depends on VIDEO_VGA_VIA_LCD
|
|
default ""
|
|
---help---
|
|
Set the enable pin for the external VGA DAC. This takes a string in the
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
config VIDEO_COMPOSITE
|
|
bool "Composite video output support"
|
|
depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
|
|
default n
|
|
---help---
|
|
Say Y here to add support for outputting composite video.
|
|
|
|
config VIDEO_LCD_MODE
|
|
string "LCD panel timing details"
|
|
depends on VIDEO
|
|
default ""
|
|
---help---
|
|
LCD panel timing details string, leave empty if there is no LCD panel.
|
|
This is in drivers/video/videomodes.c: video_get_params() format, e.g.
|
|
x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
|
|
Also see: http://linux-sunxi.org/LCD
|
|
|
|
config VIDEO_LCD_DCLK_PHASE
|
|
int "LCD panel display clock phase"
|
|
depends on VIDEO
|
|
default 1
|
|
---help---
|
|
Select LCD panel display clock phase shift, range 0-3.
|
|
|
|
config VIDEO_LCD_POWER
|
|
string "LCD panel power enable pin"
|
|
depends on VIDEO
|
|
default ""
|
|
---help---
|
|
Set the power enable pin for the LCD panel. This takes a string in the
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
config VIDEO_LCD_RESET
|
|
string "LCD panel reset pin"
|
|
depends on VIDEO
|
|
default ""
|
|
---help---
|
|
Set the reset pin for the LCD panel. This takes a string in the format
|
|
understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
config VIDEO_LCD_BL_EN
|
|
string "LCD panel backlight enable pin"
|
|
depends on VIDEO
|
|
default ""
|
|
---help---
|
|
Set the backlight enable pin for the LCD panel. This takes a string in the
|
|
the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
|
|
port H.
|
|
|
|
config VIDEO_LCD_BL_PWM
|
|
string "LCD panel backlight pwm pin"
|
|
depends on VIDEO
|
|
default ""
|
|
---help---
|
|
Set the backlight pwm pin for the LCD panel. This takes a string in the
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
config VIDEO_LCD_BL_PWM_ACTIVE_LOW
|
|
bool "LCD panel backlight pwm is inverted"
|
|
depends on VIDEO
|
|
default y
|
|
---help---
|
|
Set this if the backlight pwm output is active low.
|
|
|
|
config VIDEO_LCD_PANEL_I2C
|
|
bool "LCD panel needs to be configured via i2c"
|
|
depends on VIDEO
|
|
default n
|
|
select CMD_I2C
|
|
---help---
|
|
Say y here if the LCD panel needs to be configured via i2c. This
|
|
will add a bitbang i2c controller using gpios to talk to the LCD.
|
|
|
|
config VIDEO_LCD_PANEL_I2C_SDA
|
|
string "LCD panel i2c interface SDA pin"
|
|
depends on VIDEO_LCD_PANEL_I2C
|
|
default "PG12"
|
|
---help---
|
|
Set the SDA pin for the LCD i2c interface. This takes a string in the
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
config VIDEO_LCD_PANEL_I2C_SCL
|
|
string "LCD panel i2c interface SCL pin"
|
|
depends on VIDEO_LCD_PANEL_I2C
|
|
default "PG10"
|
|
---help---
|
|
Set the SCL pin for the LCD i2c interface. This takes a string in the
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
|
|
|
|
|
|
# Note only one of these may be selected at a time! But hidden choices are
|
|
# not supported by Kconfig
|
|
config VIDEO_LCD_IF_PARALLEL
|
|
bool
|
|
|
|
config VIDEO_LCD_IF_LVDS
|
|
bool
|
|
|
|
|
|
choice
|
|
prompt "LCD panel support"
|
|
depends on VIDEO
|
|
---help---
|
|
Select which type of LCD panel to support.
|
|
|
|
config VIDEO_LCD_PANEL_PARALLEL
|
|
bool "Generic parallel interface LCD panel"
|
|
select VIDEO_LCD_IF_PARALLEL
|
|
|
|
config VIDEO_LCD_PANEL_LVDS
|
|
bool "Generic lvds interface LCD panel"
|
|
select VIDEO_LCD_IF_LVDS
|
|
|
|
config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
|
|
bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
|
|
select VIDEO_LCD_SSD2828
|
|
select VIDEO_LCD_IF_PARALLEL
|
|
---help---
|
|
7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
|
|
|
|
config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
|
|
bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
|
|
select VIDEO_LCD_ANX9804
|
|
select VIDEO_LCD_IF_PARALLEL
|
|
select VIDEO_LCD_PANEL_I2C
|
|
---help---
|
|
Select this for eDP LCD panels with 4 lanes running at 1.62G,
|
|
connected via an ANX9804 bridge chip.
|
|
|
|
config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
|
|
bool "Hitachi tx18d42vm LCD panel"
|
|
select VIDEO_LCD_HITACHI_TX18D42VM
|
|
select VIDEO_LCD_IF_LVDS
|
|
---help---
|
|
7.85" 1024x768 Hitachi tx18d42vm LCD panel support
|
|
|
|
config VIDEO_LCD_TL059WV5C0
|
|
bool "tl059wv5c0 LCD panel"
|
|
select VIDEO_LCD_PANEL_I2C
|
|
select VIDEO_LCD_IF_PARALLEL
|
|
---help---
|
|
6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
|
|
Aigo M60/M608/M606 tablets.
|
|
|
|
endchoice
|
|
|
|
config SATAPWR
|
|
string "SATA power pin"
|
|
default ""
|
|
help
|
|
Set the pins used to power the SATA. This takes a string in the
|
|
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
|
|
port H.
|
|
|
|
config GMAC_TX_DELAY
|
|
int "GMAC Transmit Clock Delay Chain"
|
|
default 0
|
|
---help---
|
|
Set the GMAC Transmit Clock Delay Chain value.
|
|
|
|
config SPL_STACK_R_ADDR
|
|
default 0x4fe00000 if MACH_SUN4I
|
|
default 0x4fe00000 if MACH_SUN5I
|
|
default 0x4fe00000 if MACH_SUN6I
|
|
default 0x4fe00000 if MACH_SUN7I
|
|
default 0x4fe00000 if MACH_SUN8I
|
|
default 0x2fe00000 if MACH_SUN9I
|
|
default 0x4fe00000 if MACH_SUN50I
|
|
|
|
endif
|