mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-25 04:23:46 +00:00
736 lines
14 KiB
Text
736 lines
14 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* dts file for Xilinx ZynqMP ZCU102 RevA
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*
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* (C) Copyright 2015 - 2018, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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model = "ZynqMP ZCU102 RevA";
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compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
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aliases {
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ethernet0 = &gem3;
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gpio0 = &gpio;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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mmc0 = &sdhci1;
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rtc0 = &rtc;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &dcc;
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spi0 = &qspi;
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usb0 = &usb0;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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xlnx,eeprom = &eeprom;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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sw19 {
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label = "sw19";
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gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
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linux,code = <KEY_DOWN>;
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gpio-key,wakeup;
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autorepeat;
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};
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};
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leds {
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compatible = "gpio-leds";
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heartbeat_led {
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label = "heartbeat";
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gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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ina226-u76 {
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compatible = "iio-hwmon";
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io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
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};
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ina226-u77 {
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compatible = "iio-hwmon";
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io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
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};
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ina226-u78 {
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compatible = "iio-hwmon";
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io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
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};
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ina226-u87 {
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compatible = "iio-hwmon";
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io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
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};
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ina226-u85 {
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compatible = "iio-hwmon";
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io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
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};
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ina226-u86 {
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compatible = "iio-hwmon";
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io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
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};
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ina226-u93 {
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compatible = "iio-hwmon";
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io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
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};
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ina226-u88 {
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compatible = "iio-hwmon";
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io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
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};
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ina226-u15 {
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compatible = "iio-hwmon";
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io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
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};
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ina226-u92 {
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compatible = "iio-hwmon";
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io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
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};
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ina226-u79 {
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compatible = "iio-hwmon";
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io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
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};
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ina226-u81 {
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compatible = "iio-hwmon";
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io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
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};
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ina226-u80 {
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compatible = "iio-hwmon";
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io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
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};
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ina226-u84 {
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compatible = "iio-hwmon";
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io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
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};
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ina226-u16 {
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compatible = "iio-hwmon";
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io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
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};
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ina226-u65 {
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compatible = "iio-hwmon";
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io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
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};
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ina226-u74 {
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compatible = "iio-hwmon";
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io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
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};
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ina226-u75 {
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compatible = "iio-hwmon";
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io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
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};
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};
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&can1 {
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status = "okay";
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};
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&dcc {
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status = "okay";
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};
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&fpd_dma_chan1 {
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status = "okay";
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};
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&fpd_dma_chan2 {
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status = "okay";
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};
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&fpd_dma_chan3 {
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status = "okay";
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};
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&fpd_dma_chan4 {
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status = "okay";
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};
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&fpd_dma_chan5 {
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status = "okay";
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};
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&fpd_dma_chan6 {
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status = "okay";
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};
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&fpd_dma_chan7 {
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status = "okay";
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};
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&fpd_dma_chan8 {
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status = "okay";
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};
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&gem3 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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phy0: ethernet-phy@21 {
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reg = <21>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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ti,dp83867-rxctrl-strap-quirk;
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/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
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};
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};
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&gpio {
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status = "okay";
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};
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&gpu {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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tca6416_u97: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller; /* IRQ not connected */
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#gpio-cells = <2>;
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gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
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"PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
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"", "", "", "", "", "", "", "", "";
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gtr_sel0 {
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gpio-hog;
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gpios = <0 0>;
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output-low; /* PCIE = 0, DP = 1 */
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line-name = "sel0";
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};
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gtr_sel1 {
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gpio-hog;
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gpios = <1 0>;
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output-high; /* PCIE = 0, DP = 1 */
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line-name = "sel1";
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};
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gtr_sel2 {
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gpio-hog;
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gpios = <2 0>;
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output-high; /* PCIE = 0, USB0 = 1 */
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line-name = "sel2";
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};
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gtr_sel3 {
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gpio-hog;
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gpios = <3 0>;
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output-high; /* PCIE = 0, SATA = 1 */
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line-name = "sel3";
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};
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};
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tca6416_u61: gpio@21 {
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compatible = "ti,tca6416";
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reg = <0x21>;
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gpio-controller; /* IRQ not connected */
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#gpio-cells = <2>;
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gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
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"PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
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"PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
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"PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
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};
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i2c-mux@75 { /* u60 */
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compatible = "nxp,pca9544";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x75>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/* PS_PMBUS */
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u76: ina226@40 { /* u76 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u76";
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reg = <0x40>;
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shunt-resistor = <5000>;
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};
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u77: ina226@41 { /* u77 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u77";
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reg = <0x41>;
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shunt-resistor = <5000>;
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};
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u78: ina226@42 { /* u78 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u78";
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reg = <0x42>;
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shunt-resistor = <5000>;
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};
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u87: ina226@43 { /* u87 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u87";
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reg = <0x43>;
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shunt-resistor = <5000>;
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};
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u85: ina226@44 { /* u85 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u85";
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reg = <0x44>;
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shunt-resistor = <5000>;
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};
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u86: ina226@45 { /* u86 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u86";
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reg = <0x45>;
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shunt-resistor = <5000>;
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};
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u93: ina226@46 { /* u93 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u93";
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reg = <0x46>;
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shunt-resistor = <5000>;
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};
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u88: ina226@47 { /* u88 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u88";
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reg = <0x47>;
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shunt-resistor = <5000>;
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};
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u15: ina226@4a { /* u15 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u15";
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reg = <0x4a>;
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shunt-resistor = <5000>;
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};
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u92: ina226@4b { /* u92 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u92";
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reg = <0x4b>;
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shunt-resistor = <5000>;
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};
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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/* PL_PMBUS */
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u79: ina226@40 { /* u79 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u79";
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reg = <0x40>;
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shunt-resistor = <2000>;
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};
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u81: ina226@41 { /* u81 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u81";
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reg = <0x41>;
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shunt-resistor = <5000>;
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};
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u80: ina226@42 { /* u80 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u80";
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reg = <0x42>;
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shunt-resistor = <5000>;
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};
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u84: ina226@43 { /* u84 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u84";
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reg = <0x43>;
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shunt-resistor = <5000>;
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};
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u16: ina226@44 { /* u16 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u16";
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reg = <0x44>;
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shunt-resistor = <5000>;
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};
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u65: ina226@45 { /* u65 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u65";
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reg = <0x45>;
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shunt-resistor = <5000>;
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};
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u74: ina226@46 { /* u74 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u74";
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reg = <0x46>;
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shunt-resistor = <5000>;
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};
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u75: ina226@47 { /* u75 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-u75";
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reg = <0x47>;
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shunt-resistor = <5000>;
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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/* MAXIM_PMBUS - 00 */
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max15301@a { /* u46 */
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compatible = "maxim,max15301";
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reg = <0xa>;
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};
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max15303@b { /* u4 */
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compatible = "maxim,max15303";
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reg = <0xb>;
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};
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max15303@10 { /* u13 */
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compatible = "maxim,max15303";
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reg = <0x10>;
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};
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max15301@13 { /* u47 */
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compatible = "maxim,max15301";
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reg = <0x13>;
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};
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max15303@14 { /* u7 */
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compatible = "maxim,max15303";
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reg = <0x14>;
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};
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max15303@15 { /* u6 */
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compatible = "maxim,max15303";
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reg = <0x15>;
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};
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max15303@16 { /* u10 */
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compatible = "maxim,max15303";
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reg = <0x16>;
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};
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max15303@17 { /* u9 */
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compatible = "maxim,max15303";
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reg = <0x17>;
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};
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max15301@18 { /* u63 */
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compatible = "maxim,max15301";
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reg = <0x18>;
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};
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max15303@1a { /* u49 */
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compatible = "maxim,max15303";
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reg = <0x1a>;
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};
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max15303@1d { /* u18 */
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compatible = "maxim,max15303";
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reg = <0x1d>;
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};
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max15303@20 { /* u8 */
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compatible = "maxim,max15303";
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status = "disabled"; /* unreachable */
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reg = <0x20>;
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};
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max20751@72 { /* u95 */
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compatible = "maxim,max20751";
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reg = <0x72>;
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};
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max20751@73 { /* u96 */
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compatible = "maxim,max20751";
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reg = <0x73>;
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};
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};
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/* Bus 3 is not connected */
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};
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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/* PL i2c via PCA9306 - u45 */
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i2c-mux@74 { /* u34 */
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x74>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/*
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* IIC_EEPROM 1kB memory which uses 256B blocks
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* where every block has different address.
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* 0 - 256B address 0x54
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* 256B - 512B address 0x55
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* 512B - 768B address 0x56
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* 768B - 1024B address 0x57
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*/
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eeprom: eeprom@54 { /* u23 */
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compatible = "atmel,24c08";
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reg = <0x54>;
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};
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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si5341: clock-generator@36 { /* SI5341 - u69 */
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compatible = "silabs,si5341";
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reg = <0x36>;
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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si570_1: clock-generator@5d { /* USER SI570 - u42 */
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#clock-cells = <0>;
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compatible = "silabs,si570";
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reg = <0x5d>;
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temperature-stability = <50>;
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factory-fout = <300000000>;
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clock-frequency = <300000000>;
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clock-output-names = "si570_user";
|
|
};
|
|
};
|
|
i2c@3 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <3>;
|
|
si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
|
|
#clock-cells = <0>;
|
|
compatible = "silabs,si570";
|
|
reg = <0x5d>;
|
|
temperature-stability = <50>; /* copy from zc702 */
|
|
factory-fout = <156250000>;
|
|
clock-frequency = <148500000>;
|
|
clock-output-names = "si570_mgt";
|
|
};
|
|
};
|
|
i2c@4 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <4>;
|
|
si5328: clock-generator@69 {/* SI5328 - u20 */
|
|
compatible = "silabs,si5328";
|
|
reg = <0x69>;
|
|
/*
|
|
* Chip has interrupt present connected to PL
|
|
* interrupt-parent = <&>;
|
|
* interrupts = <>;
|
|
*/
|
|
};
|
|
};
|
|
/* 5 - 7 unconnected */
|
|
};
|
|
|
|
i2c-mux@75 {
|
|
compatible = "nxp,pca9548"; /* u135 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x75>;
|
|
|
|
i2c@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
/* HPC0_IIC */
|
|
};
|
|
i2c@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
/* HPC1_IIC */
|
|
};
|
|
i2c@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <2>;
|
|
/* SYSMON */
|
|
};
|
|
i2c@3 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <3>;
|
|
/* DDR4 SODIMM */
|
|
};
|
|
i2c@4 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <4>;
|
|
/* SEP 3 */
|
|
};
|
|
i2c@5 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <5>;
|
|
/* SEP 2 */
|
|
};
|
|
i2c@6 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <6>;
|
|
/* SEP 1 */
|
|
};
|
|
i2c@7 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <7>;
|
|
/* SEP 0 */
|
|
};
|
|
};
|
|
};
|
|
|
|
&pcie {
|
|
status = "okay";
|
|
};
|
|
|
|
&qspi {
|
|
status = "okay";
|
|
is-dual = <1>;
|
|
flash@0 {
|
|
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x0>;
|
|
spi-tx-bus-width = <1>;
|
|
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
|
|
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
|
partition@qspi-fsbl-uboot { /* for testing purpose */
|
|
label = "qspi-fsbl-uboot";
|
|
reg = <0x0 0x100000>;
|
|
};
|
|
partition@qspi-linux { /* for testing purpose */
|
|
label = "qspi-linux";
|
|
reg = <0x100000 0x500000>;
|
|
};
|
|
partition@qspi-device-tree { /* for testing purpose */
|
|
label = "qspi-device-tree";
|
|
reg = <0x600000 0x20000>;
|
|
};
|
|
partition@qspi-rootfs { /* for testing purpose */
|
|
label = "qspi-rootfs";
|
|
reg = <0x620000 0x5E0000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&rtc {
|
|
status = "okay";
|
|
};
|
|
|
|
&sata {
|
|
status = "okay";
|
|
/* SATA OOB timing settings */
|
|
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
|
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
|
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
|
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
|
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
|
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
|
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
|
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
|
phy-names = "sata-phy";
|
|
phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
|
|
};
|
|
|
|
/* SD1 with level shifter */
|
|
&sdhci1 {
|
|
status = "okay";
|
|
no-1-8-v; /* for 1.0 silicon */
|
|
xlnx,mio_bank = <1>;
|
|
};
|
|
|
|
&serdes {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart1 {
|
|
status = "okay";
|
|
};
|
|
|
|
/* ULPI SMSC USB3320 */
|
|
&usb0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&dwc3_0 {
|
|
status = "okay";
|
|
dr_mode = "host";
|
|
snps,usb3_lpm_capable;
|
|
phy-names = "usb3-phy";
|
|
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
|
|
maximum-speed = "super-speed";
|
|
};
|
|
|
|
&watchdog0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&xilinx_ams {
|
|
status = "okay";
|
|
};
|
|
|
|
&ams_ps {
|
|
status = "okay";
|
|
};
|
|
|
|
&ams_pl {
|
|
status = "okay";
|
|
};
|
|
|
|
&xilinx_drm {
|
|
status = "okay";
|
|
clocks = <&si570_1>;
|
|
};
|
|
|
|
&xlnx_dp {
|
|
status = "okay";
|
|
};
|
|
|
|
&xlnx_dp_sub {
|
|
status = "okay";
|
|
xlnx,vid-clk-pl;
|
|
};
|
|
|
|
&xlnx_dp_snd_pcm0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&xlnx_dp_snd_pcm1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&xlnx_dp_snd_card {
|
|
status = "okay";
|
|
};
|
|
|
|
&xlnx_dp_snd_codec0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&xlnx_dpdma {
|
|
status = "okay";
|
|
};
|