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988b3fa08d
ID code was added by commit ddf8deabc3 ("arm64: zynqmp: Add support for
SVD devices") based on documentation but after receiving part new ID code
came up. That's why fix IDcode to match xck24 module.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7b39aeeec211458ba4132a10beb7ad295eedb87f.1674030324.git.michal.simek@amd.com
360 lines
7.7 KiB
C
360 lines
7.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Xilinx ZynqMP SOC driver
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*
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* Copyright (C) 2021 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*
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* Copyright (C) 2022 Weidmüller Interface GmbH & Co. KG
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* Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <asm/cache.h>
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#include <soc.h>
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#include <zynqmp_firmware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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/*
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* Zynqmp has 4 silicon revisions
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* v0 -> 0(XCZU9EG-ES1)
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* v1 -> 1(XCZU3EG-ES1, XCZU15EG-ES1)
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* v2 -> 2(XCZU7EV-ES1, XCZU9EG-ES2, XCZU19EG-ES1)
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* v3 -> 3(Production Level)
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*/
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static const char zynqmp_family[] = "ZynqMP";
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#define EFUSE_VCU_DIS_SHIFT 8
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#define EFUSE_VCU_DIS_MASK BIT(EFUSE_VCU_DIS_SHIFT)
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#define EFUSE_GPU_DIS_SHIFT 5
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#define EFUSE_GPU_DIS_MASK BIT(EFUSE_GPU_DIS_SHIFT)
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#define IDCODE_DEV_TYPE_MASK GENMASK(27, 0)
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#define IDCODE2_PL_INIT_SHIFT 9
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#define IDCODE2_PL_INIT_MASK BIT(IDCODE2_PL_INIT_SHIFT)
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#define ZYNQMP_VERSION_SIZE 7
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enum {
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ZYNQMP_VARIANT_EG = BIT(0),
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ZYNQMP_VARIANT_EV = BIT(1),
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ZYNQMP_VARIANT_CG = BIT(2),
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ZYNQMP_VARIANT_DR = BIT(3),
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};
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struct zynqmp_device {
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u32 id;
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u8 device;
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u8 variants;
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};
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struct soc_xilinx_zynqmp_priv {
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const char *family;
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char machine[ZYNQMP_VERSION_SIZE];
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char revision;
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};
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static const struct zynqmp_device zynqmp_devices[] = {
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{
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.id = 0x04688093,
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.device = 1,
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.variants = ZYNQMP_VARIANT_EG,
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},
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{
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.id = 0x04711093,
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.device = 2,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
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},
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{
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.id = 0x04710093,
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.device = 3,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
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},
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{
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.id = 0x04721093,
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.device = 4,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
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ZYNQMP_VARIANT_EV,
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},
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{
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.id = 0x04720093,
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.device = 5,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
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ZYNQMP_VARIANT_EV,
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},
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{
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.id = 0x04739093,
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.device = 6,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
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},
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{
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.id = 0x04730093,
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.device = 7,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
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ZYNQMP_VARIANT_EV,
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},
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{
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.id = 0x04738093,
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.device = 9,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
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},
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{
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.id = 0x04740093,
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.device = 11,
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.variants = ZYNQMP_VARIANT_EG,
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},
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{
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.id = 0x04750093,
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.device = 15,
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.variants = ZYNQMP_VARIANT_EG,
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},
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{
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.id = 0x04759093,
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.device = 17,
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.variants = ZYNQMP_VARIANT_EG,
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},
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{
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.id = 0x04758093,
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.device = 19,
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.variants = ZYNQMP_VARIANT_EG,
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},
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{
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.id = 0x047E1093,
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.device = 21,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047E3093,
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.device = 23,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047E5093,
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.device = 25,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047E4093,
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.device = 27,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047E0093,
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.device = 28,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047E2093,
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.device = 29,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047E6093,
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.device = 39,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047FD093,
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.device = 43,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047F8093,
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.device = 46,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047FF093,
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.device = 47,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047FB093,
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.device = 48,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047FE093,
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.device = 49,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x046d0093,
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.device = 67,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x04712093,
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.device = 24,
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.variants = 0,
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},
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{
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.id = 0x04724093,
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.device = 26,
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.variants = 0,
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},
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};
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static const struct zynqmp_device *zynqmp_get_device(u32 idcode)
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{
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idcode &= IDCODE_DEV_TYPE_MASK;
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for (int i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
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if (zynqmp_devices[i].id == idcode)
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return &zynqmp_devices[i];
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}
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return NULL;
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}
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static int soc_xilinx_zynqmp_detect_machine(struct udevice *dev, u32 idcode,
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u32 idcode2)
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{
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struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
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const struct zynqmp_device *device;
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int ret;
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device = zynqmp_get_device(idcode);
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if (!device)
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return 0;
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/* Add device prefix to the name */
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ret = snprintf(priv->machine, sizeof(priv->machine), "%s%d",
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device->variants ? "zu" : "xck", device->device);
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if (ret < 0)
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return ret;
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if (device->variants & ZYNQMP_VARIANT_EV) {
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/* Devices with EV variant might be EG/CG/EV family */
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if (idcode2 & IDCODE2_PL_INIT_MASK) {
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u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
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EFUSE_VCU_DIS_SHIFT) << 1 |
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((idcode2 & EFUSE_GPU_DIS_MASK) >>
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EFUSE_GPU_DIS_SHIFT);
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/*
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* Get family name based on extended idcode values as
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* determined on UG1087, EXTENDED_IDCODE register
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* description
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*/
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switch (family) {
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case 0x00:
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strlcat(priv->machine, "ev",
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sizeof(priv->machine));
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break;
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case 0x10:
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strlcat(priv->machine, "eg",
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sizeof(priv->machine));
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break;
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case 0x11:
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strlcat(priv->machine, "cg",
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sizeof(priv->machine));
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break;
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default:
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/* Do not append family name*/
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break;
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}
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} else {
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/*
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* When PL powered down the VCU Disable efuse cannot be
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* read. So, ignore the bit and just findout if it is CG
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* or EG/EV variant.
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*/
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strlcat(priv->machine, (idcode2 & EFUSE_GPU_DIS_MASK) ?
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"cg" : "e", sizeof(priv->machine));
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}
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} else if (device->variants & ZYNQMP_VARIANT_CG) {
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/* Devices with CG variant might be EG or CG family */
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strlcat(priv->machine, (idcode2 & EFUSE_GPU_DIS_MASK) ?
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"cg" : "eg", sizeof(priv->machine));
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} else if (device->variants & ZYNQMP_VARIANT_EG) {
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strlcat(priv->machine, "eg", sizeof(priv->machine));
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} else if (device->variants & ZYNQMP_VARIANT_DR) {
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strlcat(priv->machine, "dr", sizeof(priv->machine));
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}
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return 0;
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}
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static int soc_xilinx_zynqmp_get_family(struct udevice *dev, char *buf, int size)
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{
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struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
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return snprintf(buf, size, "%s", priv->family);
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}
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static int soc_xilinx_zynqmp_get_machine(struct udevice *dev, char *buf, int size)
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{
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struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
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const char *machine = priv->machine;
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if (!machine[0])
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machine = "unknown";
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return snprintf(buf, size, "%s", machine);
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}
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static int soc_xilinx_zynqmp_get_revision(struct udevice *dev, char *buf, int size)
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{
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struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
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return snprintf(buf, size, "v%d", priv->revision);
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}
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static const struct soc_ops soc_xilinx_zynqmp_ops = {
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.get_family = soc_xilinx_zynqmp_get_family,
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.get_revision = soc_xilinx_zynqmp_get_revision,
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.get_machine = soc_xilinx_zynqmp_get_machine,
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};
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static int soc_xilinx_zynqmp_probe(struct udevice *dev)
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{
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struct soc_xilinx_zynqmp_priv *priv = dev_get_priv(dev);
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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priv->family = zynqmp_family;
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if (!IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE))
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ret = zynqmp_mmio_read(ZYNQMP_PS_VERSION, &ret_payload[2]);
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else
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ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0,
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ret_payload);
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if (ret < 0)
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return ret;
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priv->revision = ret_payload[2] & ZYNQMP_PS_VER_MASK;
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if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) {
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/*
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* Firmware returns:
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* payload[0][31:0] = status of the operation
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* payload[1] = IDCODE
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* payload[2][19:0] = Version
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* payload[2][28:20] = EXTENDED_IDCODE
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* payload[2][29] = PL_INIT
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*/
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u32 idcode = ret_payload[1];
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u32 idcode2 = ret_payload[2] >>
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ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
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dev_dbg(dev, "IDCODE: 0x%0x, IDCODE2: 0x%0x\n", idcode,
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idcode2);
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ret = soc_xilinx_zynqmp_detect_machine(dev, idcode, idcode2);
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if (ret)
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return ret;
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}
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return 0;
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}
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U_BOOT_DRIVER(soc_xilinx_zynqmp) = {
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.name = "soc_xilinx_zynqmp",
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.id = UCLASS_SOC,
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.ops = &soc_xilinx_zynqmp_ops,
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.probe = soc_xilinx_zynqmp_probe,
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.priv_auto = sizeof(struct soc_xilinx_zynqmp_priv),
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.flags = DM_FLAG_PRE_RELOC,
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};
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