mirror of
https://github.com/AsahiLinux/u-boot
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5c32de202b
This patch added Kconfig support for CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET and enabled it in respective defconfig. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
267 lines
8.3 KiB
Text
267 lines
8.3 KiB
Text
#
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# Multifunction miscellaneous devices
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#
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menu "Multifunction device drivers"
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config MISC
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bool "Enable Driver Model for Misc drivers"
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depends on DM
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help
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Enable driver model for miscellaneous devices. This class is
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used only for those do not fit other more general classes. A
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set of generic read, write and ioctl methods may be used to
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access the device.
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config ALTERA_SYSID
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bool "Altera Sysid support"
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depends on MISC
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help
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Select this to enable a sysid for Altera devices. Please find
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details on the "Embedded Peripherals IP User Guide" of Altera.
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config ATSHA204A
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bool "Support for Atmel ATSHA204A module"
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depends on MISC
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help
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Enable support for I2C connected Atmel's ATSHA204A
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CryptoAuthentication module found for example on the Turris Omnia
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board.
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config ROCKCHIP_EFUSE
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bool "Rockchip e-fuse support"
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depends on MISC
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help
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Enable (read-only) access for the e-fuse block found in Rockchip
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SoCs: accesses can either be made using byte addressing and a length
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or through child-nodes that are generated based on the e-fuse map
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retrieved from the DTS.
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This driver currently supports the RK3399 only, but can easily be
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extended (by porting the read function from the Linux kernel sources)
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to support other recent Rockchip devices.
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config CMD_CROS_EC
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bool "Enable crosec command"
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depends on CROS_EC
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help
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Enable command-line access to the Chrome OS EC (Embedded
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Controller). This provides the 'crosec' command which has
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a number of sub-commands for performing EC tasks such as
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updating its flash, accessing a small saved context area
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and talking to the I2C bus behind the EC (if there is one).
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config CROS_EC
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bool "Enable Chrome OS EC"
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help
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Enable access to the Chrome OS EC. This is a separate
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microcontroller typically available on a SPI bus on Chromebooks. It
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provides access to the keyboard, some internal storage and may
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control access to the battery and main PMIC depending on the
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device. You can use the 'crosec' command to access it.
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config CROS_EC_I2C
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bool "Enable Chrome OS EC I2C driver"
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depends on CROS_EC
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help
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Enable I2C access to the Chrome OS EC. This is used on older
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ARM Chromebooks such as snow and spring before the standard bus
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changed to SPI. The EC will accept commands across the I2C using
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a special message protocol, and provide responses.
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config CROS_EC_LPC
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bool "Enable Chrome OS EC LPC driver"
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depends on CROS_EC
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help
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Enable I2C access to the Chrome OS EC. This is used on x86
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Chromebooks such as link and falco. The keyboard is provided
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through a legacy port interface, so on x86 machines the main
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function of the EC is power and thermal management.
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config CROS_EC_SANDBOX
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bool "Enable Chrome OS EC sandbox driver"
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depends on CROS_EC && SANDBOX
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help
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Enable a sandbox emulation of the Chrome OS EC. This supports
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keyboard (use the -l flag to enable the LCD), verified boot context,
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EC flash read/write/erase support and a few other things. It is
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enough to perform a Chrome OS verified boot on sandbox.
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config CROS_EC_SPI
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bool "Enable Chrome OS EC SPI driver"
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depends on CROS_EC
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help
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Enable SPI access to the Chrome OS EC. This is used on newer
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ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
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provides a faster and more robust interface than I2C but the bugs
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are less interesting.
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config DS4510
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bool "Enable support for DS4510 CPU supervisor"
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help
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Enable support for the Maxim DS4510 CPU supervisor. It has an
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integrated 64-byte EEPROM, four programmable non-volatile I/O pins
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and a configurable timer for the supervisor function. The device is
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connected over I2C.
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config FSL_SEC_MON
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bool "Enable FSL SEC_MON Driver"
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help
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Freescale Security Monitor block is responsible for monitoring
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system states.
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Security Monitor can be transitioned on any security failures,
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like software violations or hardware security violations.
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config MXC_OCOTP
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bool "Enable MXC OCOTP Driver"
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help
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If you say Y here, you will get support for the One Time
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Programmable memory pages that are stored on the some
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Freescale i.MX processors.
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config NUVOTON_NCT6102D
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bool "Enable Nuvoton NCT6102D Super I/O driver"
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help
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If you say Y here, you will get support for the Nuvoton
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NCT6102D Super I/O driver. This can be used to enable or
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disable the legacy UART, the watchdog or other devices
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in the Nuvoton Super IO chips on X86 platforms.
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config PWRSEQ
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bool "Enable power-sequencing drivers"
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depends on DM
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help
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Power-sequencing drivers provide support for controlling power for
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devices. They are typically referenced by a phandle from another
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device. When the device is started up, its power sequence can be
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initiated.
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config SPL_PWRSEQ
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bool "Enable power-sequencing drivers for SPL"
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depends on PWRSEQ
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help
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Power-sequencing drivers provide support for controlling power for
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devices. They are typically referenced by a phandle from another
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device. When the device is started up, its power sequence can be
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initiated.
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config PCA9551_LED
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bool "Enable PCA9551 LED driver"
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help
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Enable driver for PCA9551 LED controller. This controller
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is connected via I2C. So I2C needs to be enabled.
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config PCA9551_I2C_ADDR
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hex "I2C address of PCA9551 LED controller"
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depends on PCA9551_LED
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default 0x60
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help
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The I2C address of the PCA9551 LED controller.
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config STM32_RCC
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bool "Enable RCC driver for the STM32 SoC's family"
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depends on STM32 && MISC
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help
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Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
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block) is responsible of the management of the clock and reset
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generation.
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This driver is similar to an MFD driver in the Linux kernel.
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config TEGRA_CAR
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bool "Enable support for the Tegra CAR driver"
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depends on TEGRA_NO_BPMP
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help
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The Tegra CAR (Clock and Reset Controller) is a HW module that
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controls almost all clocks and resets in a Tegra SoC.
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config TEGRA186_BPMP
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bool "Enable support for the Tegra186 BPMP driver"
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depends on TEGRA186
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help
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The Tegra BPMP (Boot and Power Management Processor) is a separate
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auxiliary CPU embedded into Tegra to perform power management work,
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and controls related features such as clocks, resets, power domains,
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PMIC I2C bus, etc. This driver provides the core low-level
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communication path by which feature-specific drivers (such as clock)
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can make requests to the BPMP. This driver is similar to an MFD
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driver in the Linux kernel.
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config WINBOND_W83627
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bool "Enable Winbond Super I/O driver"
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help
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If you say Y here, you will get support for the Winbond
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W83627 Super I/O driver. This can be used to enable the
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legacy UART or other devices in the Winbond Super IO chips
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on X86 platforms.
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config QFW
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bool
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help
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Hidden option to enable QEMU fw_cfg interface. This will be selected by
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either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
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config I2C_EEPROM
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bool "Enable driver for generic I2C-attached EEPROMs"
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depends on MISC
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help
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Enable a generic driver for EEPROMs attached via I2C.
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config SPL_I2C_EEPROM
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bool "Enable driver for generic I2C-attached EEPROMs for SPL"
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depends on MISC && SPL && SPL_DM
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help
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This option is an SPL-variant of the I2C_EEPROM option.
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See the help of I2C_EEPROM for details.
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config ZYNQ_GEM_I2C_MAC_OFFSET
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hex "Set the I2C MAC offset"
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default 0x0
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help
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Set the MAC offset for i2C.
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if I2C_EEPROM
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config SYS_I2C_EEPROM_ADDR
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hex "Chip address of the EEPROM device"
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default 0
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config SYS_I2C_EEPROM_BUS
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int "I2C bus of the EEPROM device."
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default 0
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config SYS_EEPROM_SIZE
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int "Size in bytes of the EEPROM device"
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default 256
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config SYS_EEPROM_PAGE_WRITE_BITS
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int "Number of bits used to address bytes in a single page"
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default 0
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help
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The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
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A 64 byte page, for example would require six bits.
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config SYS_EEPROM_PAGE_WRITE_DELAY_MS
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int "Number of milliseconds to delay between page writes"
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default 0
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config SYS_I2C_EEPROM_ADDR_LEN
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int "Length in bytes of the EEPROM memory array address"
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default 1
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help
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Note: This is NOT the chip address length!
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config SYS_I2C_EEPROM_ADDR_OVERFLOW
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hex "EEPROM Address Overflow"
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default 0
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help
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EEPROM chips that implement "address overflow" are ones
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like Catalyst 24WC04/08/16 which has 9/10/11 bits of
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address and the extra bits end up in the "chip address" bit
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slots. This makes a 24WC08 (1Kbyte) chip look like four 256
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byte chips.
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endif
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endmenu
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