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72a087e047
Patch by Haavard Skinnemoen, 06 Sep 2006 This patch adds support for the AT32AP CPU family and the AT32AP7000 chip, which is the first chip implementing the AVR32 architecture. The AT32AP CPU core is a high-performance implementation featuring a 7-stage pipeline, separate instruction- and data caches, and a MMU. For more information, please see the "AVR32 AP Technical Reference": http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf In addition to this, the AT32AP7000 chip comes with a large set of integrated peripherals, many of which are shared with the AT91 series of ARM-based microcontrollers from Atmel. Full data sheet is available here: http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
65 lines
1.7 KiB
ArmAsm
65 lines
1.7 KiB
ArmAsm
/*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/sysreg.h>
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#include <asm/ptrace.h>
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.section .text.exception,"ax"
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.global _evba
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.type _evba,@function
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.align 10
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_evba:
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.irp x,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16
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.align 2
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rjmp unknown_exception
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.endr
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.global timer_interrupt_handler
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.type timer_interrupt_handler,@function
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.align 2
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timer_interrupt_handler:
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/*
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* Increment timer_overflow and re-write COMPARE with 0xffffffff.
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*
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* We're running at interrupt level 3, so we don't need to save
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* r8-r12 or lr to the stack.
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*/
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mov r8, lo(timer_overflow)
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orh r8, hi(timer_overflow)
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ld.w r9, r8[0]
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mov r10, -1
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mtsr SYSREG_COMPARE, r10
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sub r9, -1
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st.w r8[0], r9
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rete
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.type unknown_exception, @function
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unknown_exception:
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pushm r0-r12
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sub r8, sp, REG_R12 - REG_R0 - 4
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mov r9, lr
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mfsr r10, SYSREG_RAR_EX
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mfsr r11, SYSREG_RSR_EX
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pushm r8-r11
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mfsr r12, SYSREG_ECR
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mov r11, sp
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rcall do_unknown_exception
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1: rjmp 1b
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