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858e5a1a8b
Add FSP_UINT64 read support as preparation for FSP-M and FSP-S parameter update. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org>
111 lines
3.1 KiB
C
111 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2019 Google LLC
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* Copyright 2020 B&R Industrial Automation GmbH - http://www.br-automation.com
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*/
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#ifndef __ASM_ARCH_FSP_BINDINGS_H
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#define __ASM_ARCH_FSP_BINDINGS_H
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#include <asm/arch/fsp/fsp_m_upd.h>
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#include <asm/arch/fsp/fsp_s_upd.h>
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#define ARRAY_SIZE_OF_MEMBER(s, m) (ARRAY_SIZE((((s *)0)->m)))
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#define SIZE_OF_MEMBER(s, m) (sizeof((((s *)0)->m)))
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enum conf_type {
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FSP_UINT8,
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FSP_UINT16,
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FSP_UINT32,
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FSP_UINT64,
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FSP_STRING,
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FSP_LPDDR4_SWIZZLE,
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};
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/**
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* struct fsp_binding - Binding describing devicetree/FSP relationships
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* @offset: Offset within the FSP config structure
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* @propname: Name of property to read
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* @type: Type of the property to read
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* @count: If the property is expected to be an array, this is the
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* number of expected elements
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* Set to 0 if the property is expected to be a scalar
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*
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* The struct fsp_binding is used to describe the relationship between
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* values stored in devicetree and where they are placed in the FSP
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* configuration structure.
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*/
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struct fsp_binding {
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size_t offset;
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char *propname;
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enum conf_type type;
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size_t count;
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};
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/*
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* LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation.
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* There are four physical LPDDR4 channels, each 32-bits wide. There are two
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* logical channels using two physical channels together to form a 64-bit
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* interface to memory for each logical channel.
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*/
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enum {
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LP4_PHYS_CH0A,
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LP4_PHYS_CH0B,
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LP4_PHYS_CH1A,
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LP4_PHYS_CH1B,
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LP4_NUM_PHYS_CHANNELS,
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};
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/*
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* The DQs within a physical channel can be bit-swizzled within each byte.
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* Within a channel the bytes can be swapped, but the DQs need to be routed
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* with the corresponding DQS (strobe).
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*/
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enum {
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LP4_DQS0,
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LP4_DQS1,
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LP4_DQS2,
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LP4_DQS3,
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LP4_NUM_BYTE_LANES,
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DQ_BITS_PER_DQS = 8,
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};
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/* Provide bit swizzling per DQS and byte swapping within a channel */
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struct lpddr4_chan_swizzle_cfg {
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u8 dqs[LP4_NUM_BYTE_LANES][DQ_BITS_PER_DQS];
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};
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struct lpddr4_swizzle_cfg {
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struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS];
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};
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/**
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* fsp_m_update_config_from_dtb() - Read FSP-M config from devicetree node
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* @node: Valid node reference to read property from
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* @cfg: Pointer to FSP-M config structure
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* @return 0 on success, -ve on error
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*
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* This function reads the configuration for FSP-M from the provided
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* devicetree node and saves it in the FSP-M configuration structure.
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* Configuration options that are not present in the devicetree are
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* left at their current value.
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*/
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int fsp_m_update_config_from_dtb(ofnode node, struct fsp_m_config *cfg);
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/**
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* fsp_s_update_config_from_dtb() - Read FSP-S config from devicetree node
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* @node: Valid node reference to read property from
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* @cfg: Pointer to FSP-S config structure
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* @return 0 on success, -ve on error
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*
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* This function reads the configuration for FSP-S from the provided
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* devicetree node and saves it in the FSP-S configuration structure.
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* Configuration options that are not present in the devicetree are
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* left at their current value.
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*/
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int fsp_s_update_config_from_dtb(ofnode node, struct fsp_s_config *cfg);
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#endif
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