mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 21:54:01 +00:00
57a72d0560
Correct the SPDX tag format.
Fixes: 3b52847a45 ("Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze")
Signed-off-by: Tom Rini <trini@konsulko.com>
138 lines
4.8 KiB
C
138 lines
4.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Michal Simek <michals@xilinx.com>
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* Copyright (C) 2015 Nathan Rossi <nathan@nathanrossi.com>
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*
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* The following Boot Header format/structures and values are defined in the
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* following documents:
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* * ug1085 ZynqMP TRM doc v1.4 (Chapter 11, Table 11-4)
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* * ug1137 ZynqMP Software Developer Guide v6.0 (Chapter 16)
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*/
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#ifndef _ZYNQMPIMAGE_H_
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#define _ZYNQMPIMAGE_H_
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#include <stdint.h>
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#define HEADER_INTERRUPT_DEFAULT (cpu_to_le32(0xeafffffe))
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#define HEADER_REGINIT_NULL (cpu_to_le32(0xffffffff))
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#define HEADER_WIDTHDETECTION (cpu_to_le32(0xaa995566))
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#define HEADER_IMAGEIDENTIFIER (cpu_to_le32(0x584c4e58))
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#define HEADER_CPU_SELECT_MASK (0x3 << 10)
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#define HEADER_CPU_SELECT_R5_SINGLE (0x0 << 10)
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#define HEADER_CPU_SELECT_A53_32BIT (0x1 << 10)
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#define HEADER_CPU_SELECT_A53_64BIT (0x2 << 10)
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#define HEADER_CPU_SELECT_R5_DUAL (0x3 << 10)
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enum {
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ENCRYPTION_EFUSE = 0xa5c3c5a3,
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ENCRYPTION_OEFUSE = 0xa5c3c5a7,
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ENCRYPTION_BBRAM = 0x3a5c3c5a,
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ENCRYPTION_OBBRAM = 0xa35c7ca5,
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ENCRYPTION_NONE = 0x0,
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};
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struct zynqmp_reginit {
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uint32_t address;
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uint32_t data;
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};
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#define HEADER_INTERRUPT_VECTORS 8
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#define HEADER_REGINITS 256
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struct image_header_table {
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uint32_t version; /* 0x00 */
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uint32_t nr_parts; /* 0x04 */
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uint32_t partition_header_offset; /* 0x08, divided by 4 */
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uint32_t image_header_offset; /* 0x0c, divided by 4 */
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uint32_t auth_certificate_offset; /* 0x10 */
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uint32_t boot_device; /* 0x14 */
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uint32_t __reserved1[9]; /* 0x18 - 0x38 */
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uint32_t checksum; /* 0x3c */
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};
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#define PART_ATTR_VEC_LOCATION 0x800000
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#define PART_ATTR_BS_BLOCK_SIZE_MASK 0x700000
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#define PART_ATTR_BS_BLOCK_SIZE_DEFAULT 0x000000
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#define PART_ATTR_BS_BLOCK_SIZE_8MB 0x400000
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#define PART_ATTR_BIG_ENDIAN 0x040000
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#define PART_ATTR_PART_OWNER_MASK 0x030000
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#define PART_ATTR_PART_OWNER_FSBL 0x000000
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#define PART_ATTR_PART_OWNER_UBOOT 0x010000
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#define PART_ATTR_RSA_SIG 0x008000
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#define PART_ATTR_CHECKSUM_MASK 0x007000
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#define PART_ATTR_CHECKSUM_NONE 0x000000
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#define PART_ATTR_CHECKSUM_MD5 0x001000
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#define PART_ATTR_CHECKSUM_SHA2 0x002000
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#define PART_ATTR_CHECKSUM_SHA3 0x003000
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#define PART_ATTR_DEST_CPU_SHIFT 8
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#define PART_ATTR_DEST_CPU_MASK 0x000f00
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#define PART_ATTR_DEST_CPU_NONE 0x000000
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#define PART_ATTR_DEST_CPU_A53_0 0x000100
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#define PART_ATTR_DEST_CPU_A53_1 0x000200
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#define PART_ATTR_DEST_CPU_A53_2 0x000300
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#define PART_ATTR_DEST_CPU_A53_3 0x000400
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#define PART_ATTR_DEST_CPU_R5_0 0x000500
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#define PART_ATTR_DEST_CPU_R5_1 0x000600
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#define PART_ATTR_DEST_CPU_R5_L 0x000700
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#define PART_ATTR_DEST_CPU_PMU 0x000800
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#define PART_ATTR_ENCRYPTED 0x000080
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#define PART_ATTR_DEST_DEVICE_SHIFT 4
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#define PART_ATTR_DEST_DEVICE_MASK 0x000070
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#define PART_ATTR_DEST_DEVICE_NONE 0x000000
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#define PART_ATTR_DEST_DEVICE_PS 0x000010
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#define PART_ATTR_DEST_DEVICE_PL 0x000020
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#define PART_ATTR_DEST_DEVICE_PMU 0x000030
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#define PART_ATTR_DEST_DEVICE_XIP 0x000040
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#define PART_ATTR_A53_EXEC_AARCH32 0x000008
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#define PART_ATTR_TARGET_EL_SHIFT 1
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#define PART_ATTR_TARGET_EL_MASK 0x000006
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#define PART_ATTR_TZ_SECURE 0x000001
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static const char *dest_cpus[0x10] = {
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"none", "a5x-0", "a5x-1", "a5x-2", "a5x-3", "r5-0", "r5-1",
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"r5-lockstep", "pmu", "unknown", "unknown", "unknown", "unknown",
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"unknown", "unknown", "unknown"
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};
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struct partition_header {
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uint32_t len_enc; /* 0x00, divided by 4 */
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uint32_t len_unenc; /* 0x04, divided by 4 */
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uint32_t len; /* 0x08, divided by 4 */
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uint32_t next_partition_offset; /* 0x0c */
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uint64_t entry_point; /* 0x10 */
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uint64_t load_address; /* 0x18 */
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uint32_t offset; /* 0x20, divided by 4 */
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uint32_t attributes; /* 0x24 */
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uint32_t __reserved1; /* 0x28 */
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uint32_t checksum_offset; /* 0x2c, divided by 4 */
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uint32_t __reserved2; /* 0x30 */
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uint32_t auth_certificate_offset; /* 0x34 */
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uint32_t __reserved3; /* 0x38 */
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uint32_t checksum; /* 0x3c */
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};
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struct zynqmp_header {
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uint32_t interrupt_vectors[HEADER_INTERRUPT_VECTORS]; /* 0x0 */
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uint32_t width_detection; /* 0x20 */
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uint32_t image_identifier; /* 0x24 */
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uint32_t encryption; /* 0x28 */
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uint32_t image_load; /* 0x2c */
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uint32_t image_offset; /* 0x30 */
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uint32_t pfw_image_length; /* 0x34 */
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uint32_t total_pfw_image_length; /* 0x38 */
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uint32_t image_size; /* 0x3c */
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uint32_t image_stored_size; /* 0x40 */
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uint32_t image_attributes; /* 0x44 */
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uint32_t checksum; /* 0x48 */
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uint32_t __reserved1[19]; /* 0x4c */
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uint32_t image_header_table_offset; /* 0x98 */
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uint32_t __reserved2[7]; /* 0x9c */
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struct zynqmp_reginit register_init[HEADER_REGINITS]; /* 0xb8 */
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uint32_t __reserved4[66]; /* 0x9c0 */
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};
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void zynqmpimage_default_header(struct zynqmp_header *ptr);
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void zynqmpimage_print_header(const void *ptr);
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#endif /* _ZYNQMPIMAGE_H_ */
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