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The clock parent of the AHB root clock when using mux option 1 is the SYS PLL 270MHz clock. This is specified in Table 5-11 Clock Root Table of the i.MX 7Dual Applications Processor Reference Manual. While it could be a documentation error, the 270MHz parent is also mentioned in the boot ROM configuration in Table 6-28: The clock is by default at 135MHz due to a POST_PODF value of 1 (=> divider of 2). Signed-off-by: Stefan Agner <stefan@agner.ch> |
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| .. | ||
| clock.c | ||
| clock_slice.c | ||
| Kconfig | ||
| Makefile | ||
| psci-mx7.c | ||
| psci.S | ||
| soc.c | ||