mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-08 22:24:32 +00:00
691d719db7
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
120 lines
2.4 KiB
C
120 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
|
|
*
|
|
* Based on sheevaplug.c originally written by
|
|
* Prafulla Wadaskar <prafulla@marvell.com>
|
|
* (C) Copyright 2009
|
|
* Marvell Semiconductor <www.marvell.com>
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <init.h>
|
|
#include <miiphy.h>
|
|
#include <net.h>
|
|
#include <asm/mach-types.h>
|
|
#include <asm/arch/soc.h>
|
|
#include <asm/arch/mpp.h>
|
|
#include <asm/arch/cpu.h>
|
|
#include <asm/io.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
/*
|
|
* default gpio configuration
|
|
*/
|
|
mvebu_config_gpio(NAS220_GE_OE_VAL_LOW, NAS220_GE_OE_VAL_HIGH,
|
|
NAS220_GE_OE_LOW, NAS220_GE_OE_HIGH);
|
|
|
|
/* Multi-Purpose Pins Functionality configuration */
|
|
static const u32 kwmpp_config[] = {
|
|
MPP0_NF_IO2,
|
|
MPP1_NF_IO3,
|
|
MPP2_NF_IO4,
|
|
MPP3_NF_IO5,
|
|
MPP4_NF_IO6,
|
|
MPP5_NF_IO7,
|
|
MPP6_SYSRST_OUTn,
|
|
MPP7_SPI_SCn,
|
|
MPP8_TW_SDA,
|
|
MPP9_TW_SCK,
|
|
MPP10_UART0_TXD,
|
|
MPP11_UART0_RXD,
|
|
MPP12_GPO,
|
|
MPP13_GPIO,
|
|
MPP14_GPIO,
|
|
MPP15_SATA0_ACTn,
|
|
MPP16_SATA1_ACTn,
|
|
MPP17_SATA0_PRESENTn,
|
|
MPP18_NF_IO0,
|
|
MPP19_NF_IO1,
|
|
MPP20_GPIO,
|
|
MPP21_GPIO,
|
|
MPP22_GPIO,
|
|
MPP23_GPIO,
|
|
MPP24_GPIO,
|
|
MPP25_GPIO,
|
|
MPP26_GPIO,
|
|
MPP27_GPIO,
|
|
MPP28_GPIO,
|
|
MPP29_GPIO,
|
|
MPP30_GPIO,
|
|
MPP31_GPIO,
|
|
MPP32_GPIO,
|
|
MPP33_GPIO,
|
|
MPP34_GPIO,
|
|
MPP35_GPIO,
|
|
0
|
|
};
|
|
kirkwood_mpp_conf(kwmpp_config, NULL);
|
|
return 0;
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
/*
|
|
* arch number of board
|
|
*/
|
|
gd->bd->bi_arch_number = MACH_TYPE_RD88F6192_NAS;
|
|
|
|
/* adress of boot parameters */
|
|
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_RESET_PHY_R
|
|
/* Configure and enable MV88E1116 PHY */
|
|
void reset_phy(void)
|
|
{
|
|
u16 reg;
|
|
u16 devadr;
|
|
char *name = "egiga0";
|
|
|
|
if (miiphy_set_current_dev(name))
|
|
return;
|
|
|
|
/* command to read PHY dev address */
|
|
if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
|
|
printf("Err..%s could not read PHY dev address\n", __func__);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Enable RGMII delay on Tx and Rx for CPU port
|
|
* Ref: sec 4.7.2 of chip datasheet
|
|
*/
|
|
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
|
|
miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
|
|
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
|
|
miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
|
|
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
|
|
|
|
/* reset the phy */
|
|
miiphy_reset(name, devadr);
|
|
|
|
printf("88E1116 Initialized on %s\n", name);
|
|
}
|
|
#endif /* CONFIG_RESET_PHY_R */
|