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https://github.com/AsahiLinux/u-boot
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367ff4bc84
There is xrdc inside i.MX8ULP, we need to configure permission to make sure AP non-secure world could access the resources. Signed-off-by: Peng Fan <peng.fan@nxp.com>
144 lines
2.8 KiB
C
144 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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*/
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#include <common.h>
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#include <div64.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define XRDC_ADDR 0x292f0000
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#define MRC_OFFSET 0x2000
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#define MRC_STEP 0x200
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#define SP(X) ((X) << 9)
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#define SU(X) ((X) << 6)
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#define NP(X) ((X) << 3)
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#define NU(X) ((X) << 0)
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#define RWX 7
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#define RW 6
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#define R 4
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#define X 1
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#define D7SEL_CODE (SP(RW) | SU(RW) | NP(RWX) | NU(RWX))
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#define D6SEL_CODE (SP(RW) | SU(RW) | NP(RWX))
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#define D5SEL_CODE (SP(RW) | SU(RWX))
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#define D4SEL_CODE SP(RWX)
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#define D3SEL_CODE (SP(X) | SU(X) | NP(X) | NU(X))
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#define D0SEL_CODE 0
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#define D7SEL_DAT (SP(RW) | SU(RW) | NP(RW) | NU(RW))
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#define D6SEL_DAT (SP(RW) | SU(RW) | NP(RW))
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#define D5SEL_DAT (SP(RW) | SU(RW) | NP(R) | NU(R))
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#define D4SEL_DAT (SP(RW) | SU(RW))
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#define D3SEL_DAT SP(RW)
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union dxsel_perm {
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struct {
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u8 dx;
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u8 perm;
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};
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u32 dom_perm;
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};
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int xrdc_config_mrc_dx_perm(u32 mrc_con, u32 region, u32 dom, u32 dxsel)
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{
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ulong w2_addr;
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u32 val = 0;
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w2_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20 + 0x8;
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val = (readl(w2_addr) & (~(7 << (3 * dom)))) | (dxsel << (3 * dom));
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writel(val, w2_addr);
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return 0;
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}
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int xrdc_config_mrc_w0_w1(u32 mrc_con, u32 region, u32 w0, u32 size)
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{
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ulong w0_addr, w1_addr;
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w0_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20;
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w1_addr = w0_addr + 4;
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if ((size % 32) != 0)
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return -EINVAL;
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writel(w0 & ~0x1f, w0_addr);
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writel(w0 + size - 1, w1_addr);
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return 0;
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}
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int xrdc_config_mrc_w3_w4(u32 mrc_con, u32 region, u32 w3, u32 w4)
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{
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ulong w3_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20 + 0xC;
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ulong w4_addr = w3_addr + 4;
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writel(w3, w3_addr);
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writel(w4, w4_addr);
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return 0;
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}
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int xrdc_config_pdac_openacc(u32 bridge, u32 index)
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{
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ulong w0_addr;
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u32 val;
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switch (bridge) {
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case 3:
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w0_addr = XRDC_ADDR + 0x1000 + 0x8 * index;
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break;
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case 4:
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w0_addr = XRDC_ADDR + 0x1400 + 0x8 * index;
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break;
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case 5:
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w0_addr = XRDC_ADDR + 0x1800 + 0x8 * index;
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break;
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default:
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return -EINVAL;
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}
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writel(0xffffff, w0_addr);
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val = readl(w0_addr + 4);
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writel(val | BIT(31), w0_addr + 4);
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return 0;
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}
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int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm)
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{
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ulong w0_addr;
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u32 val;
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switch (bridge) {
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case 3:
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w0_addr = XRDC_ADDR + 0x1000 + 0x8 * index;
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break;
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case 4:
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w0_addr = XRDC_ADDR + 0x1400 + 0x8 * index;
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break;
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case 5:
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w0_addr = XRDC_ADDR + 0x1800 + 0x8 * index;
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break;
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default:
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return -EINVAL;
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}
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val = readl(w0_addr);
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writel((val & ~(0x7 << (dom * 3))) | (perm << (dom * 3)), w0_addr);
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val = readl(w0_addr + 4);
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writel(val | BIT(31), w0_addr + 4);
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return 0;
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}
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