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Marek Vasut b3d97f8ce3 ARM: stm32: Power cycle Buck3 in reset on DHSOM 
In case the DHSOM is in suspend state and either reset button is pushed
or IWDG2 triggers a watchdog reset, then DRAM initialization could fail
as follows:

  "
  RAM: DDR3L 32bits 2x4Gb 533MHz
  DDR invalid size : 0x4, expected 0x40000000
  DRAM init failed: -22
  ### ERROR ### Please RESET the board ###
  "

Avoid this failure by not keeping any Buck regulators enabled during reset,
let the SoC and DRAMs power cycle fully. Since the change which keeps Buck3
VDD enabled during reset is ST specific, move this addition to ST specific
SPL board initialization so that it wouldn't affect the DHSOM .

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2023-08-16 15:19:57 +02:00
..
debug_uart.c stm32mp: fix compilation issue with DEBUG_UART 2022-10-18 08:40:59 +02:00
extlinux.conf stm32mp1: add example files for FIT generation 2019-08-27 11:19:23 +02:00
fit_copro_kernel_dtb.its board: st: stm32mp1: update load address for FIT examples 2020-11-25 14:27:19 +01:00
fit_kernel_dtb.its board: st: stm32mp1: update load address for FIT examples 2020-11-25 14:27:19 +01:00
Kconfig arm: stm32mp: add support of STM32MP13x 2022-06-17 09:58:21 +02:00
MAINTAINERS configs: add stm32mp13 defconfig 2022-06-17 10:41:16 +02:00
Makefile stm32mp: fix compilation issue with DEBUG_UART 2022-10-18 08:40:59 +02:00
README doc: add board documentation for stm32mp1 2020-03-02 09:41:32 +01:00
spl.c ARM: stm32: Power cycle Buck3 in reset on DHSOM 2023-08-16 15:19:57 +02:00
stm32mp1.c board: stm32mp1: use fdt_copy_fixed_partitions 2023-06-16 11:01:16 +02:00

README 

see doc/board/st/stm32mp1.rst