mirror of
https://github.com/AsahiLinux/u-boot
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229 lines
6 KiB
C
229 lines
6 KiB
C
/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/immap.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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puts("Board: ");
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puts("Freescale M54455 EVB\n");
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return 0;
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};
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phys_size_t initdram(int board_type)
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{
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u32 dramsize;
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#ifdef CONFIG_CF_SBF
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/*
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* Serial Boot: The dram is already initialized in start.S
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* only require to return DRAM size
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*/
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dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
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#else
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sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
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gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
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u32 i;
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dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
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for (i = 0x13; i < 0x20; i++) {
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if (dramsize == (1 << i))
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break;
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}
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i--;
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out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
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out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
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out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i);
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out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
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out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
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/* Issue PALL */
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out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
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/* Issue LEMR */
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out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
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out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300);
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udelay(500);
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/* Issue PALL */
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out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
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/* Perform two refresh cycles */
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out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
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out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
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out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200);
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out_be32(&sdram->sdcr,
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(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
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udelay(100);
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#endif
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return (dramsize << 1);
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};
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int testdram(void)
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{
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/* TODO: XXX XXX XXX */
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printf("DRAM test not implemented!\n");
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return (0);
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}
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#if defined(CONFIG_CMD_IDE)
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#include <ata.h>
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int ide_preinit(void)
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{
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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u32 tmp;
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tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
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setbits_8(&gpio->par_fec, tmp);
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tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) |
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(GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
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setbits_be16(&gpio->par_feci2c, tmp);
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setbits_be16(&gpio->par_ata,
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GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
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GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 |
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GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
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GPIO_PAR_ATA_IORDY_IORDY);
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setbits_be16(&gpio->par_pci,
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GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
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return (0);
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}
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void ide_set_reset(int idereset)
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{
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atac_t *ata = (atac_t *) MMAP_ATA;
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long period;
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/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
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int piotms[5][9] = {
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{70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
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{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
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{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
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{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
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{25, 70, 20, 10, 20, 5, 10, 0, 35}
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}; /* PIO 4 */
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if (idereset) {
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/* control reset */
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out_8(&ata->cr, 0);
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udelay(10000);
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} else {
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#define CALC_TIMING(t) (t + period - 1) / period
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period = 1000000000 / gd->bus_clk; /* period in ns */
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/*ata->ton = CALC_TIMING (180); */
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out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
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out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
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out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
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out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
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out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
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out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
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out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
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/* IORDY enable */
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out_8(&ata->cr, 0x40);
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udelay(200000);
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/* IORDY enable */
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setbits_8(&ata->cr, 0x01);
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}
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}
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#endif
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#if defined(CONFIG_PCI)
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/*
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* Initialize PCI devices, report devices found.
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*/
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static struct pci_controller hose;
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extern void pci_mcf5445x_init(struct pci_controller *hose);
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void pci_init_board(void)
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{
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pci_mcf5445x_init(&hose);
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}
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_FLASH_CFI_LEGACY)
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#include <flash.h>
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ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
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{
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int sect[] = CONFIG_SYS_ATMEL_SECT;
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int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
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int i, j, k;
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if (base != CONFIG_SYS_ATMEL_BASE)
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return 0;
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info->flash_id = 0x01000000;
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info->portwidth = 1;
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info->chipwidth = 1;
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info->buffer_size = 1;
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info->erase_blk_tout = 16384;
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info->write_tout = 2;
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info->buffer_write_tout = 5;
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info->vendor = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
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info->cmd_reset = 0x00F0;
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info->interface = FLASH_CFI_X8;
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info->legacy_unlock = 0;
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info->manufacturer_id = (u16) ATM_MANUFACT;
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info->device_id = ATM_ID_LV040;
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info->device_id2 = 0;
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info->ext_addr = 0;
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info->cfi_version = 0x3133;
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info->cfi_offset = 0x0000;
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info->addr_unlock1 = 0x00000555;
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info->addr_unlock2 = 0x000002AA;
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info->name = "CFI conformant";
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info->size = 0;
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info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT;
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info->start[0] = base;
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for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
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info->size += sect[i] * sectsz[i];
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for (j = 0; j < sect[i]; j++, k++) {
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info->start[k + 1] = info->start[k] + sectsz[i];
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info->protect[k] = 0;
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}
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}
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return 1;
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}
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#endif /* CONFIG_SYS_FLASH_CFI */
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