mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 10:48:51 +00:00
127e57c671
Update the H6 DT files from the Linux 5.12 release. The changes are minimal (many LED node renames), but also help to enable USB port 0 in U-Boot (later), enable the RSB device (not yet used in U-Boot), and also introduce an MMC frequency limit. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
1058 lines
26 KiB
Text
1058 lines
26 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun50i-h6-ccu.h>
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#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
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#include <dt-bindings/clock/sun8i-de2.h>
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#include <dt-bindings/clock/sun8i-tcon-top.h>
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#include <dt-bindings/reset/sun50i-h6-ccu.h>
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#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
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#include <dt-bindings/reset/sun8i-de2.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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#cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <2>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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#cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <3>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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#cooling-cells = <2>;
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};
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};
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de: display-engine {
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compatible = "allwinner,sun50i-h6-display-engine";
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allwinner,pipelines = <&mixer0>;
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status = "disabled";
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};
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osc24M: osc24M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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arm,no-tick-in-suspend;
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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bus@1000000 {
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compatible = "allwinner,sun50i-h6-de3",
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"allwinner,sun50i-a64-de2";
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reg = <0x1000000 0x400000>;
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allwinner,sram = <&de2_sram 1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x1000000 0x400000>;
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display_clocks: clock@0 {
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compatible = "allwinner,sun50i-h6-de3-clk";
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reg = <0x0 0x10000>;
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clocks = <&ccu CLK_DE>,
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<&ccu CLK_BUS_DE>;
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clock-names = "mod",
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"bus";
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resets = <&ccu RST_BUS_DE>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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mixer0: mixer@100000 {
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compatible = "allwinner,sun50i-h6-de3-mixer-0";
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reg = <0x100000 0x100000>;
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clocks = <&display_clocks CLK_BUS_MIXER0>,
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<&display_clocks CLK_MIXER0>;
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clock-names = "bus",
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"mod";
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resets = <&display_clocks RST_MIXER0>;
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iommus = <&iommu 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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mixer0_out: port@1 {
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reg = <1>;
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mixer0_out_tcon_top_mixer0: endpoint {
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remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
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};
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};
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};
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};
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};
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video-codec@1c0e000 {
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compatible = "allwinner,sun50i-h6-video-engine";
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reg = <0x01c0e000 0x2000>;
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clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
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<&ccu CLK_MBUS_VE>;
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clock-names = "ahb", "mod", "ram";
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resets = <&ccu RST_BUS_VE>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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allwinner,sram = <&ve_sram 1>;
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iommus = <&iommu 3>;
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};
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gpu: gpu@1800000 {
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compatible = "allwinner,sun50i-h6-mali",
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"arm,mali-t720";
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reg = <0x01800000 0x4000>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "job", "mmu", "gpu";
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clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
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clock-names = "core", "bus";
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resets = <&ccu RST_BUS_GPU>;
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status = "disabled";
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};
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crypto: crypto@1904000 {
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compatible = "allwinner,sun50i-h6-crypto";
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reg = <0x01904000 0x1000>;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>;
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clock-names = "bus", "mod", "ram";
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resets = <&ccu RST_BUS_CE>;
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};
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syscon: syscon@3000000 {
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compatible = "allwinner,sun50i-h6-system-control",
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"allwinner,sun50i-a64-system-control";
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reg = <0x03000000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram_c: sram@28000 {
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compatible = "mmio-sram";
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reg = <0x00028000 0x1e000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00028000 0x1e000>;
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de2_sram: sram-section@0 {
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compatible = "allwinner,sun50i-h6-sram-c",
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"allwinner,sun50i-a64-sram-c";
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reg = <0x0000 0x1e000>;
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};
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};
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sram_c1: sram@1a00000 {
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compatible = "mmio-sram";
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reg = <0x01a00000 0x200000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x01a00000 0x200000>;
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ve_sram: sram-section@0 {
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compatible = "allwinner,sun50i-h6-sram-c1",
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"allwinner,sun4i-a10-sram-c1";
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reg = <0x000000 0x200000>;
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};
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};
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};
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ccu: clock@3001000 {
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compatible = "allwinner,sun50i-h6-ccu";
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reg = <0x03001000 0x1000>;
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clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
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clock-names = "hosc", "losc", "iosc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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dma: dma-controller@3002000 {
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compatible = "allwinner,sun50i-h6-dma";
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reg = <0x03002000 0x1000>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
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clock-names = "bus", "mbus";
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dma-channels = <16>;
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dma-requests = <46>;
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resets = <&ccu RST_BUS_DMA>;
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#dma-cells = <1>;
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};
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msgbox: mailbox@3003000 {
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compatible = "allwinner,sun50i-h6-msgbox",
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"allwinner,sun6i-a31-msgbox";
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reg = <0x03003000 0x1000>;
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clocks = <&ccu CLK_BUS_MSGBOX>;
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resets = <&ccu RST_BUS_MSGBOX>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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};
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sid: efuse@3006000 {
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compatible = "allwinner,sun50i-h6-sid";
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reg = <0x03006000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ths_calibration: thermal-sensor-calibration@14 {
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reg = <0x14 0x8>;
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};
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cpu_speed_grade: cpu-speed-grade@1c {
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reg = <0x1c 0x4>;
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};
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};
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watchdog: watchdog@30090a0 {
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compatible = "allwinner,sun50i-h6-wdt",
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"allwinner,sun6i-a31-wdt";
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reg = <0x030090a0 0x20>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc24M>;
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/* Broken on some H6 boards */
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status = "disabled";
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};
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pwm: pwm@300a000 {
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compatible = "allwinner,sun50i-h6-pwm";
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reg = <0x0300a000 0x400>;
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clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
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clock-names = "mod", "bus";
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resets = <&ccu RST_BUS_PWM>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pio: pinctrl@300b000 {
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compatible = "allwinner,sun50i-h6-pinctrl";
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reg = <0x0300b000 0x400>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <3>;
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ext_rgmii_pins: rgmii-pins {
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pins = "PD0", "PD1", "PD2", "PD3", "PD4",
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"PD5", "PD7", "PD8", "PD9", "PD10",
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"PD11", "PD12", "PD13", "PD19", "PD20";
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function = "emac";
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drive-strength = <40>;
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};
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hdmi_pins: hdmi-pins {
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pins = "PH8", "PH9", "PH10";
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function = "hdmi";
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};
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i2c0_pins: i2c0-pins {
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pins = "PD25", "PD26";
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function = "i2c0";
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};
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i2c1_pins: i2c1-pins {
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pins = "PH5", "PH6";
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function = "i2c1";
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};
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i2c2_pins: i2c2-pins {
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pins = "PD23", "PD24";
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function = "i2c2";
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};
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mmc0_pins: mmc0-pins {
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pins = "PF0", "PF1", "PF2", "PF3",
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"PF4", "PF5";
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function = "mmc0";
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drive-strength = <30>;
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bias-pull-up;
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};
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/omit-if-no-ref/
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mmc1_pins: mmc1-pins {
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pins = "PG0", "PG1", "PG2", "PG3",
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"PG4", "PG5";
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function = "mmc1";
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drive-strength = <30>;
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bias-pull-up;
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};
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mmc2_pins: mmc2-pins {
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pins = "PC1", "PC4", "PC5", "PC6",
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"PC7", "PC8", "PC9", "PC10",
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"PC11", "PC12", "PC13", "PC14";
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function = "mmc2";
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drive-strength = <30>;
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bias-pull-up;
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};
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/omit-if-no-ref/
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spi0_pins: spi0-pins {
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pins = "PC0", "PC2", "PC3";
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function = "spi0";
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};
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/* pin shared with MMC2-CMD (eMMC) */
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/omit-if-no-ref/
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spi0_cs_pin: spi0-cs-pin {
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pins = "PC5";
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function = "spi0";
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};
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/omit-if-no-ref/
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spi1_pins: spi1-pins {
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pins = "PH4", "PH5", "PH6";
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function = "spi1";
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};
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/omit-if-no-ref/
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spi1_cs_pin: spi1-cs-pin {
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pins = "PH3";
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function = "spi1";
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};
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spdif_tx_pin: spdif-tx-pin {
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pins = "PH7";
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function = "spdif";
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};
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uart0_ph_pins: uart0-ph-pins {
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pins = "PH0", "PH1";
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function = "uart0";
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};
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uart1_pins: uart1-pins {
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pins = "PG6", "PG7";
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function = "uart1";
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};
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uart1_rts_cts_pins: uart1-rts-cts-pins {
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pins = "PG8", "PG9";
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function = "uart1";
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};
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};
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gic: interrupt-controller@3021000 {
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compatible = "arm,gic-400";
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reg = <0x03021000 0x1000>,
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<0x03022000 0x2000>,
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<0x03024000 0x2000>,
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<0x03026000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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iommu: iommu@30f0000 {
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compatible = "allwinner,sun50i-h6-iommu";
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reg = <0x030f0000 0x10000>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_IOMMU>;
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resets = <&ccu RST_BUS_IOMMU>;
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#iommu-cells = <1>;
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};
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mmc0: mmc@4020000 {
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compatible = "allwinner,sun50i-h6-mmc",
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"allwinner,sun50i-a64-mmc";
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reg = <0x04020000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC0>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins>;
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max-frequency = <150000000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@4021000 {
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compatible = "allwinner,sun50i-h6-mmc",
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"allwinner,sun50i-a64-mmc";
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reg = <0x04021000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC1>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins>;
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max-frequency = <150000000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@4022000 {
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compatible = "allwinner,sun50i-h6-emmc",
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"allwinner,sun50i-a64-emmc";
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reg = <0x04022000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC2>;
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reset-names = "ahb";
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|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc2_pins>;
|
|
max-frequency = <150000000>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
uart0: serial@5000000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x05000000 0x400>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART0>;
|
|
resets = <&ccu RST_BUS_UART0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@5000400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x05000400 0x400>;
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART1>;
|
|
resets = <&ccu RST_BUS_UART1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@5000800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x05000800 0x400>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART2>;
|
|
resets = <&ccu RST_BUS_UART2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@5000c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x05000c00 0x400>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&ccu CLK_BUS_UART3>;
|
|
resets = <&ccu RST_BUS_UART3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@5002000 {
|
|
compatible = "allwinner,sun50i-h6-i2c",
|
|
"allwinner,sun6i-a31-i2c";
|
|
reg = <0x05002000 0x400>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_I2C0>;
|
|
resets = <&ccu RST_BUS_I2C0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c@5002400 {
|
|
compatible = "allwinner,sun50i-h6-i2c",
|
|
"allwinner,sun6i-a31-i2c";
|
|
reg = <0x05002400 0x400>;
|
|
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_I2C1>;
|
|
resets = <&ccu RST_BUS_I2C1>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c2: i2c@5002800 {
|
|
compatible = "allwinner,sun50i-h6-i2c",
|
|
"allwinner,sun6i-a31-i2c";
|
|
reg = <0x05002800 0x400>;
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_I2C2>;
|
|
resets = <&ccu RST_BUS_I2C2>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
spi0: spi@5010000 {
|
|
compatible = "allwinner,sun50i-h6-spi",
|
|
"allwinner,sun8i-h3-spi";
|
|
reg = <0x05010000 0x1000>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma 22>, <&dma 22>;
|
|
dma-names = "rx", "tx";
|
|
resets = <&ccu RST_BUS_SPI0>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
spi1: spi@5011000 {
|
|
compatible = "allwinner,sun50i-h6-spi",
|
|
"allwinner,sun8i-h3-spi";
|
|
reg = <0x05011000 0x1000>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma 23>, <&dma 23>;
|
|
dma-names = "rx", "tx";
|
|
resets = <&ccu RST_BUS_SPI1>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
emac: ethernet@5020000 {
|
|
compatible = "allwinner,sun50i-h6-emac",
|
|
"allwinner,sun50i-a64-emac";
|
|
syscon = <&syscon>;
|
|
reg = <0x05020000 0x10000>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
resets = <&ccu RST_BUS_EMAC>;
|
|
reset-names = "stmmaceth";
|
|
clocks = <&ccu CLK_BUS_EMAC>;
|
|
clock-names = "stmmaceth";
|
|
status = "disabled";
|
|
|
|
mdio: mdio {
|
|
compatible = "snps,dwmac-mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
i2s1: i2s@5091000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun50i-h6-i2s";
|
|
reg = <0x05091000 0x1000>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
|
|
clock-names = "apb", "mod";
|
|
dmas = <&dma 4>, <&dma 4>;
|
|
resets = <&ccu RST_BUS_I2S1>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
spdif: spdif@5093000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "allwinner,sun50i-h6-spdif";
|
|
reg = <0x05093000 0x400>;
|
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
|
|
clock-names = "apb", "spdif";
|
|
resets = <&ccu RST_BUS_SPDIF>;
|
|
dmas = <&dma 2>;
|
|
dma-names = "tx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spdif_tx_pin>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2otg: usb@5100000 {
|
|
compatible = "allwinner,sun50i-h6-musb",
|
|
"allwinner,sun8i-a33-musb";
|
|
reg = <0x05100000 0x0400>;
|
|
clocks = <&ccu CLK_BUS_OTG>;
|
|
resets = <&ccu RST_BUS_OTG>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "mc";
|
|
phys = <&usb2phy 0>;
|
|
phy-names = "usb";
|
|
extcon = <&usb2phy 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2phy: phy@5100400 {
|
|
compatible = "allwinner,sun50i-h6-usb-phy";
|
|
reg = <0x05100400 0x24>,
|
|
<0x05101800 0x4>,
|
|
<0x05311800 0x4>;
|
|
reg-names = "phy_ctrl",
|
|
"pmu0",
|
|
"pmu3";
|
|
clocks = <&ccu CLK_USB_PHY0>,
|
|
<&ccu CLK_USB_PHY3>;
|
|
clock-names = "usb0_phy",
|
|
"usb3_phy";
|
|
resets = <&ccu RST_USB_PHY0>,
|
|
<&ccu RST_USB_PHY3>;
|
|
reset-names = "usb0_reset",
|
|
"usb3_reset";
|
|
status = "disabled";
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
ehci0: usb@5101000 {
|
|
compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
|
|
reg = <0x05101000 0x100>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_OHCI0>,
|
|
<&ccu CLK_BUS_EHCI0>,
|
|
<&ccu CLK_USB_OHCI0>;
|
|
resets = <&ccu RST_BUS_OHCI0>,
|
|
<&ccu RST_BUS_EHCI0>;
|
|
phys = <&usb2phy 0>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci0: usb@5101400 {
|
|
compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
|
|
reg = <0x05101400 0x100>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_OHCI0>,
|
|
<&ccu CLK_USB_OHCI0>;
|
|
resets = <&ccu RST_BUS_OHCI0>;
|
|
phys = <&usb2phy 0>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
dwc3: usb@5200000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x05200000 0x10000>;
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_XHCI>,
|
|
<&ccu CLK_BUS_XHCI>,
|
|
<&rtc 0>;
|
|
clock-names = "ref", "bus_early", "suspend";
|
|
resets = <&ccu RST_BUS_XHCI>;
|
|
/*
|
|
* The datasheet of the chip doesn't declare the
|
|
* peripheral function, and there's no boards known
|
|
* to have a USB Type-B port routed to the port.
|
|
* In addition, no one has tested the peripheral
|
|
* function yet.
|
|
* So set the dr_mode to "host" in the DTSI file.
|
|
*/
|
|
dr_mode = "host";
|
|
phys = <&usb3phy>;
|
|
phy-names = "usb3-phy";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb3phy: phy@5210000 {
|
|
compatible = "allwinner,sun50i-h6-usb3-phy";
|
|
reg = <0x5210000 0x10000>;
|
|
clocks = <&ccu CLK_USB_PHY1>;
|
|
resets = <&ccu RST_USB_PHY1>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ehci3: usb@5311000 {
|
|
compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
|
|
reg = <0x05311000 0x100>;
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_OHCI3>,
|
|
<&ccu CLK_BUS_EHCI3>,
|
|
<&ccu CLK_USB_OHCI3>;
|
|
resets = <&ccu RST_BUS_OHCI3>,
|
|
<&ccu RST_BUS_EHCI3>;
|
|
phys = <&usb2phy 3>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci3: usb@5311400 {
|
|
compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
|
|
reg = <0x05311400 0x100>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_OHCI3>,
|
|
<&ccu CLK_USB_OHCI3>;
|
|
resets = <&ccu RST_BUS_OHCI3>;
|
|
phys = <&usb2phy 3>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
hdmi: hdmi@6000000 {
|
|
compatible = "allwinner,sun50i-h6-dw-hdmi";
|
|
reg = <0x06000000 0x10000>;
|
|
reg-io-width = <1>;
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
|
|
<&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
|
|
<&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
|
|
clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
|
|
"hdcp-bus";
|
|
resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
|
|
reset-names = "ctrl", "hdcp";
|
|
phys = <&hdmi_phy>;
|
|
phy-names = "phy";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hdmi_pins>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
hdmi_in: port@0 {
|
|
reg = <0>;
|
|
|
|
hdmi_in_tcon_top: endpoint {
|
|
remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
|
|
};
|
|
};
|
|
|
|
hdmi_out: port@1 {
|
|
reg = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
hdmi_phy: hdmi-phy@6010000 {
|
|
compatible = "allwinner,sun50i-h6-hdmi-phy";
|
|
reg = <0x06010000 0x10000>;
|
|
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
|
|
clock-names = "bus", "mod";
|
|
resets = <&ccu RST_BUS_HDMI>;
|
|
reset-names = "phy";
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
tcon_top: tcon-top@6510000 {
|
|
compatible = "allwinner,sun50i-h6-tcon-top";
|
|
reg = <0x06510000 0x1000>;
|
|
clocks = <&ccu CLK_BUS_TCON_TOP>,
|
|
<&ccu CLK_TCON_TV0>;
|
|
clock-names = "bus",
|
|
"tcon-tv0";
|
|
clock-output-names = "tcon-top-tv0";
|
|
resets = <&ccu RST_BUS_TCON_TOP>;
|
|
#clock-cells = <1>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
tcon_top_mixer0_in: port@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
|
|
tcon_top_mixer0_in_mixer0: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
|
|
};
|
|
};
|
|
|
|
tcon_top_mixer0_out: port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
|
|
tcon_top_mixer0_out_tcon_tv: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
|
|
};
|
|
};
|
|
|
|
tcon_top_hdmi_in: port@4 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <4>;
|
|
|
|
tcon_top_hdmi_in_tcon_tv: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&tcon_tv_out_tcon_top>;
|
|
};
|
|
};
|
|
|
|
tcon_top_hdmi_out: port@5 {
|
|
reg = <5>;
|
|
|
|
tcon_top_hdmi_out_hdmi: endpoint {
|
|
remote-endpoint = <&hdmi_in_tcon_top>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
tcon_tv: lcd-controller@6515000 {
|
|
compatible = "allwinner,sun50i-h6-tcon-tv",
|
|
"allwinner,sun8i-r40-tcon-tv";
|
|
reg = <0x06515000 0x1000>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_TCON_TV0>,
|
|
<&tcon_top CLK_TCON_TOP_TV0>;
|
|
clock-names = "ahb",
|
|
"tcon-ch1";
|
|
resets = <&ccu RST_BUS_TCON_TV0>;
|
|
reset-names = "lcd";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
tcon_tv_in: port@0 {
|
|
reg = <0>;
|
|
|
|
tcon_tv_in_tcon_top_mixer0: endpoint {
|
|
remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
|
|
};
|
|
};
|
|
|
|
tcon_tv_out: port@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
|
|
tcon_tv_out_tcon_top: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
rtc: rtc@7000000 {
|
|
compatible = "allwinner,sun50i-h6-rtc";
|
|
reg = <0x07000000 0x400>;
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-output-names = "osc32k", "osc32k-out", "iosc";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
r_ccu: clock@7010000 {
|
|
compatible = "allwinner,sun50i-h6-r-ccu";
|
|
reg = <0x07010000 0x400>;
|
|
clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
|
|
<&ccu CLK_PLL_PERIPH0>;
|
|
clock-names = "hosc", "losc", "iosc", "pll-periph";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
r_watchdog: watchdog@7020400 {
|
|
compatible = "allwinner,sun50i-h6-wdt",
|
|
"allwinner,sun6i-a31-wdt";
|
|
reg = <0x07020400 0x20>;
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&osc24M>;
|
|
};
|
|
|
|
r_intc: interrupt-controller@7021000 {
|
|
compatible = "allwinner,sun50i-h6-r-intc",
|
|
"allwinner,sun6i-a31-r-intc";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x07021000 0x400>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
r_pio: pinctrl@7022000 {
|
|
compatible = "allwinner,sun50i-h6-r-pinctrl";
|
|
reg = <0x07022000 0x400>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
|
|
clock-names = "apb", "hosc", "losc";
|
|
gpio-controller;
|
|
#gpio-cells = <3>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
|
|
r_i2c_pins: r-i2c-pins {
|
|
pins = "PL0", "PL1";
|
|
function = "s_i2c";
|
|
};
|
|
|
|
r_ir_rx_pin: r-ir-rx-pin {
|
|
pins = "PL9";
|
|
function = "s_cir_rx";
|
|
};
|
|
|
|
r_rsb_pins: r-rsb-pins {
|
|
pins = "PL0", "PL1";
|
|
function = "s_rsb";
|
|
};
|
|
};
|
|
|
|
r_ir: ir@7040000 {
|
|
compatible = "allwinner,sun50i-h6-ir",
|
|
"allwinner,sun6i-a31-ir";
|
|
reg = <0x07040000 0x400>;
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&r_ccu CLK_R_APB1_IR>,
|
|
<&r_ccu CLK_IR>;
|
|
clock-names = "apb", "ir";
|
|
resets = <&r_ccu RST_R_APB1_IR>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&r_ir_rx_pin>;
|
|
status = "disabled";
|
|
};
|
|
|
|
r_i2c: i2c@7081400 {
|
|
compatible = "allwinner,sun50i-h6-i2c",
|
|
"allwinner,sun6i-a31-i2c";
|
|
reg = <0x07081400 0x400>;
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&r_ccu CLK_R_APB2_I2C>;
|
|
resets = <&r_ccu RST_R_APB2_I2C>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&r_i2c_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
r_rsb: rsb@7083000 {
|
|
compatible = "allwinner,sun8i-a23-rsb";
|
|
reg = <0x07083000 0x400>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&r_ccu CLK_R_APB2_RSB>;
|
|
clock-frequency = <3000000>;
|
|
resets = <&r_ccu RST_R_APB2_RSB>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&r_rsb_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
ths: thermal-sensor@5070400 {
|
|
compatible = "allwinner,sun50i-h6-ths";
|
|
reg = <0x05070400 0x100>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_THS>;
|
|
clock-names = "bus";
|
|
resets = <&ccu RST_BUS_THS>;
|
|
nvmem-cells = <&ths_calibration>;
|
|
nvmem-cell-names = "calibration";
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
cpu-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
thermal-sensors = <&ths 0>;
|
|
|
|
trips {
|
|
cpu_alert: cpu-alert {
|
|
temperature = <85000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
cpu-crit {
|
|
temperature = <100000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&cpu_alert>;
|
|
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpu-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
thermal-sensors = <&ths 1>;
|
|
};
|
|
};
|
|
};
|