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70cc86a630
mx5: Add clock config interface Add clock config interface support, so that we can configure CPU or DDR clock in the later init Signed-off-by: Jason Liu <jason.hui@linaro.org> Signed-off-by: Eric Miao <eric.miao@linaro.org> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
223 lines
7.8 KiB
C
223 lines
7.8 KiB
C
/*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
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#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
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#define MXC_CCM_BASE CCM_BASE_ADDR
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/* DPLL register mapping structure */
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struct mxc_pll_reg {
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u32 ctrl;
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u32 config;
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u32 op;
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u32 mfd;
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u32 mfn;
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u32 mfn_minus;
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u32 mfn_plus;
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u32 hfs_op;
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u32 hfs_mfd;
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u32 hfs_mfn;
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u32 mfn_togc;
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u32 destat;
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};
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/* Register maping of CCM*/
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struct mxc_ccm_reg {
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u32 ccr; /* 0x0000 */
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u32 ccdr;
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u32 csr;
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u32 ccsr;
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u32 cacrr; /* 0x0010*/
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u32 cbcdr;
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u32 cbcmr;
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u32 cscmr1;
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u32 cscmr2; /* 0x0020 */
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u32 cscdr1;
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u32 cs1cdr;
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u32 cs2cdr;
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u32 cdcdr; /* 0x0030 */
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u32 chscdr;
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u32 cscdr2;
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u32 cscdr3;
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u32 cscdr4; /* 0x0040 */
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u32 cwdr;
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u32 cdhipr;
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u32 cdcr;
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u32 ctor; /* 0x0050 */
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u32 clpcr;
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u32 cisr;
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u32 cimr;
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u32 ccosr; /* 0x0060 */
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u32 cgpr;
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u32 CCGR0;
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u32 CCGR1;
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u32 CCGR2; /* 0x0070 */
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u32 CCGR3;
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u32 CCGR4;
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u32 CCGR5;
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u32 CCGR6; /* 0x0080 */
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#ifdef CONFIG_MX53
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u32 CCGR7; /* 0x0084 */
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#endif
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u32 cmeor;
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};
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/* Define the bits in register CACRR */
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#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
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#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
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/* Define the bits in register CBCDR */
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#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30)
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#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
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#define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27
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#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
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#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
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#define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22
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#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
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#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19
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#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
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#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16
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#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
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#define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13
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#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
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#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
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#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
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#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
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#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
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#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6
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#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
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#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3
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#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
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#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0
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#define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7
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/* Define the bits in register CSCMR1 */
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#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30
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#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
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#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28
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#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
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#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET 26
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#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
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#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24
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#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
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#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22
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#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
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#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20
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#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
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#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
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#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
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#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16
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#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
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#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14
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#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
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#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
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#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
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#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
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#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
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#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8
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#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
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#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
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#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
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#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4
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#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
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#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2
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#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
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#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
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#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1
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/* Define the bits in register CSCDR2 */
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#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25
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#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
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#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19
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#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
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#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16
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#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
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#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9
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#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
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#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6
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#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
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#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET 0
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#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK 0x3F
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/* Define the bits in register CBCMR */
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#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
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#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
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#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12
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#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
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#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10
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#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
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#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8
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#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
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#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6
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#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
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#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4
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#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
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#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
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#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
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/* Define the bits in register CSCDR1 */
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#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22
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#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
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#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19
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#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
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#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16
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#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
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#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14
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#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
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#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11
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#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
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#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
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#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
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#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
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#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
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#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3
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#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
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#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
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#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7
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/* Define the bits in register CCDR */
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#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
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/* Define the bits in register CCGRx */
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#define MXC_CCM_CCGR_CG_MASK 0x3
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#define MXC_CCM_CCGR4_CG5_OFFSET 10
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#define MXC_CCM_CCGR4_CG6_OFFSET 12
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#define MXC_CCM_CCGR5_CG5_OFFSET 10
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#define MXC_CCM_CCGR2_CG14_OFFSET 28
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/* Define the bits in register CLPCR */
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#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
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#define MXC_DPLLC_CTL_HFSM (1 << 7)
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#define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12)
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#define MXC_DPLLC_OP_PDF_MASK 0xf
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#define MXC_DPLLC_OP_MFI_MASK (0xf << 4)
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#define MXC_DPLLC_OP_MFI_OFFSET 4
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#define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff
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#define MXC_DPLLC_MFN_MFN_MASK 0x7ffffff
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#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
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