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35e29e89a3
Enabling and disabling PCIe ports is done via address space of system controller. All 32-bit Armada SoCs use low 4 bits in SoC Control 1 Register for enabling and disabling some or more PCIe ports. Correct mapping needs to be set in particular DTS files. DT API for mvebu-reset is prepared for implementing resets also for other HW blocks, but currently only PCIe is implemented via index 0. Currently this driver is not used as PCIe ports are automatically enabled by SerDes code executed by U-Boot SPL. But this will change in followup patches. Signed-off-by: Pali Rohár <pali@kernel.org> |
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| .. | ||
| armada8k | ||
| armada3700 | ||
| include/mach | ||
| serdes | ||
| .gitignore | ||
| arm64-common.c | ||
| cpu.c | ||
| dram.c | ||
| efuse.c | ||
| gpio.c | ||
| Kconfig | ||
| kwbimage.cfg.in | ||
| lowlevel_spl.S | ||
| Makefile | ||
| mbus.c | ||
| spl.c | ||
| system-controller.c | ||
| timer.c | ||