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u-boot/board/sbc8548
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Peter Tyser a2cd50ed6e 85xx: Add CPU 2 errata workaround to all 8548 boards 
All mpc8548-based boards should implement the suggested workaround
to CPU 2 errata. Without the workaround, its possible for the
8548's core to hang while executing a msync or mbar 0 instruction
and a snoopable transaction from an I/O master tagged to make
quick forward progress is present.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2008-12-03 22:46:42 -06:00
..
config.mk mpc85xx: Add support for SBC8548 (updated) 2008-01-09 16:25:03 -06:00
ddr.c Pass dimm parameters to populate populate controller options 2008-10-18 21:54:04 +02:00
law.c rename CFG_ macros to CONFIG_SYS 2008-10-18 21:54:03 +02:00
Makefile FSL DDR: Convert sbc8548 to new DDR code. 2008-08-27 11:43:51 -05:00
sbc8548.c 85xx: Add CPU 2 errata workaround to all 8548 boards 2008-12-03 22:46:42 -06:00
tlb.c rename CFG_ macros to CONFIG_SYS 2008-10-18 21:54:03 +02:00
u-boot.lds Align end of bss by 4 bytes 2008-11-18 23:13:16 +01:00