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70dbff1f9e
There are a few boards that use hard-coded GPIO definitions in their respective defconfig files. If the GPIO's are listed in their device trees, the nop-phy can toggle the GPIO's, so the EHCI driver does not need to know anything about the GPIO's. Add functions for getting the phys and remove the GPIO toggles since the phy will now do that. Signed-off-by: Adam Ford <aford173@gmail.com>
396 lines
9.5 KiB
C
396 lines
9.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2011 Ilya Yanok, Emcraft Systems
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* (C) Copyright 2004-2008
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* Texas Instruments, <www.ti.com>
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*
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* Derived from Beagle Board code by
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* Sunil Kumar <sunilsaini05@gmail.com>
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* Shashi Ranjan <shashiranjanmca05@gmail.com>
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*
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*/
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#include <common.h>
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#include <log.h>
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#include <usb.h>
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#include <linux/delay.h>
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#include <usb/ulpi.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/ehci.h>
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#include <asm/ehci-omap.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <power/regulator.h>
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#include "ehci.h"
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static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE;
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static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE;
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static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE;
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static int omap_uhh_reset(void)
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{
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int timeout = 0;
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u32 rev;
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rev = readl(&uhh->rev);
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/* Soft RESET */
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writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);
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switch (rev) {
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case OMAP_USBHS_REV1:
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/* Wait for soft RESET to complete */
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while (!(readl(&uhh->syss) & 0x1)) {
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if (timeout > 100) {
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printf("%s: RESET timeout\n", __func__);
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return -1;
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}
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udelay(10);
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timeout++;
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}
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/* Set No-Idle, No-Standby */
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writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
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break;
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default: /* Rev. 2 onwards */
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udelay(2); /* Need to wait before accessing SYSCONFIG back */
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/* Wait for soft RESET to complete */
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while ((readl(&uhh->sysc) & 0x1)) {
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if (timeout > 100) {
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printf("%s: RESET timeout\n", __func__);
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return -1;
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}
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udelay(10);
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timeout++;
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}
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writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
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break;
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}
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return 0;
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}
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static int omap_ehci_tll_reset(void)
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{
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unsigned long init = get_timer(0);
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/* perform TLL soft reset, and wait until reset is complete */
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writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);
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/* Wait for TLL reset to complete */
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while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
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if (get_timer(init) > CONFIG_SYS_HZ) {
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debug("OMAP EHCI error: timeout resetting TLL\n");
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return -EL3RST;
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}
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return 0;
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}
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static void omap_usbhs_hsic_init(int port)
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{
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unsigned int reg;
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/* Enable channels now */
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reg = readl(&usbtll->channel_conf + port);
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setbits_le32(®, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
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| OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
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| OMAP_TLL_CHANNEL_CONF_DRVVBUS
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| OMAP_TLL_CHANNEL_CONF_CHRGVBUS
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| OMAP_TLL_CHANNEL_CONF_CHANEN));
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writel(reg, &usbtll->channel_conf + port);
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}
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#ifdef CONFIG_USB_ULPI
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static void omap_ehci_soft_phy_reset(int port)
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{
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struct ulpi_viewport ulpi_vp;
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ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
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ulpi_vp.port_num = port;
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ulpi_reset(&ulpi_vp);
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}
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#else
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static void omap_ehci_soft_phy_reset(int port)
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{
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return;
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}
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#endif
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struct ehci_omap_priv_data {
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struct ehci_ctrl ctrl;
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struct omap_ehci *ehci;
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#ifdef CONFIG_DM_REGULATOR
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struct udevice *vbus_supply;
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#endif
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enum usb_init_type init_type;
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int portnr;
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struct phy phy[OMAP_HS_USB_PORTS];
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int nports;
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};
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/*
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* Initialize the OMAP EHCI controller and PHY.
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* Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
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* See there for additional Copyrights.
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*/
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static int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
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struct udevice *dev)
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{
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int ret;
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unsigned int i, reg = 0, rev = 0;
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debug("Initializing OMAP EHCI\n");
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ret = board_usb_init(index, USB_INIT_HOST);
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if (ret < 0)
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return ret;
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/* Hold the PHY in RESET for enough time till DIR is high */
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/* Refer: ISSUE1 */
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udelay(10);
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ret = omap_uhh_reset();
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if (ret < 0)
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return ret;
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ret = omap_ehci_tll_reset();
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if (ret)
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return ret;
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writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
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OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
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OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);
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/* Put UHH in NoIdle/NoStandby mode */
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writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
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/* setup ULPI bypass and burst configurations */
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clrsetbits_le32(®, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
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(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN |
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OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN |
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OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));
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rev = readl(&uhh->rev);
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if (rev == OMAP_USBHS_REV1) {
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if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
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clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
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else
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setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
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if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
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clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
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else
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setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
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if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
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clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
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else
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setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
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} else if (rev == OMAP_USBHS_REV2) {
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clrsetbits_le32(®, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
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OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
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/* Clear port mode fields for PHY mode */
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if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
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setbits_le32(®, OMAP_P1_MODE_HSIC);
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if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
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setbits_le32(®, OMAP_P2_MODE_HSIC);
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} else if (rev == OMAP_USBHS_REV2_1) {
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clrsetbits_le32(®,
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(OMAP_P1_MODE_CLEAR |
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OMAP_P2_MODE_CLEAR |
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OMAP_P3_MODE_CLEAR),
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OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
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/* Clear port mode fields for PHY mode */
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if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
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setbits_le32(®, OMAP_P1_MODE_HSIC);
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if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
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setbits_le32(®, OMAP_P2_MODE_HSIC);
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if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
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setbits_le32(®, OMAP_P3_MODE_HSIC);
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}
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debug("OMAP UHH_REVISION 0x%x\n", rev);
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writel(reg, &uhh->hostconfig);
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for (i = 0; i < OMAP_HS_USB_PORTS; i++)
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if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
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omap_usbhs_hsic_init(i);
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/*
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* Refer ISSUE1:
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* Hold the PHY in RESET for enough time till
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* PHY is settled and ready
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*/
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udelay(10);
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/*
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* An undocumented "feature" in the OMAP3 EHCI controller,
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* causes suspended ports to be taken out of suspend when
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* the USBCMD.Run/Stop bit is cleared (for example when
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* we do ehci_bus_suspend).
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* This breaks suspend-resume if the root-hub is allowed
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* to suspend. Writing 1 to this undocumented register bit
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* disables this feature and restores normal behavior.
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*/
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writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);
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for (i = 0; i < OMAP_HS_USB_PORTS; i++)
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if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
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omap_ehci_soft_phy_reset(i);
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debug("OMAP EHCI init done\n");
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return 0;
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}
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static struct omap_usbhs_board_data usbhs_bdata = {
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.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
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.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
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.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
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};
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static void omap_usbhs_set_mode(u8 index, const char *mode)
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{
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if (!strcmp(mode, "ehci-phy"))
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usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_PHY;
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else if (!strcmp(mode, "ehci-tll"))
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usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_TLL;
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else if (!strcmp(mode, "ehci-hsic"))
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usbhs_bdata.port_mode[index] = OMAP_EHCI_PORT_MODE_HSIC;
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}
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static int omap_usbhs_probe(struct udevice *dev)
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{
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u8 i;
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const char *mode;
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char prop[11];
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/* Go through each port portX-mode to determing phy mode */
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for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
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snprintf(prop, sizeof(prop), "port%d-mode", i + 1);
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mode = dev_read_string(dev, prop);
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/* If the portX-mode exists, set the mode */
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if (mode)
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omap_usbhs_set_mode(i, mode);
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}
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return 0;
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}
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static const struct udevice_id omap_usbhs_dt_ids[] = {
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{ .compatible = "ti,usbhs-host" },
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{ }
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};
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U_BOOT_DRIVER(usb_omaphs_host) = {
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.name = "usbhs-host",
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.id = UCLASS_SIMPLE_BUS,
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.of_match = omap_usbhs_dt_ids,
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.probe = omap_usbhs_probe,
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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static int ehci_usb_of_to_plat(struct udevice *dev)
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{
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struct usb_plat *plat = dev_get_plat(dev);
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plat->init_type = USB_INIT_HOST;
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return 0;
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}
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/*
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* This driver references phys based on the USB port. If
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* the port is unused, the corresponding phy is listed as NULL
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* which generic_phy_init_bulk treats as an error, so we need
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* a custom one that tolerates empty phys
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*/
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static int omap_ehci_phy_get(struct udevice *dev)
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{
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struct ehci_omap_priv_data *priv = dev_get_priv(dev);
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int i, ret;
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for (i = 0; i < OMAP_HS_USB_PORTS; i++) {
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ret = generic_phy_get_by_index(dev, i, &priv->phy[i]);
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if (ret && ret != -ENOENT)
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return ret;
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};
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return 0;
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};
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static int omap_ehci_probe(struct udevice *dev)
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{
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struct usb_plat *plat = dev_get_plat(dev);
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struct ehci_omap_priv_data *priv = dev_get_priv(dev);
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struct ehci_hccr *hccr;
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struct ehci_hcor *hcor;
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int ret;
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priv->ehci = dev_read_addr_ptr(dev);
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priv->portnr = dev_seq(dev);
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priv->init_type = plat->init_type;
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hccr = (struct ehci_hccr *)&priv->ehci->hccapbase;
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hcor = (struct ehci_hcor *)&priv->ehci->usbcmd;
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/* Identify Phys */
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ret = omap_ehci_phy_get(dev);
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if (ret) {
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printf("Failed to get phys\n");
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return ret;
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}
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/* Register the EHCI */
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ret = ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
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if (ret) {
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printf("Failed to register EHCI\n");
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return ret;
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}
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ret = omap_ehci_hcd_init(0, &usbhs_bdata, dev);
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if (ret)
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return ret;
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return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
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}
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static const struct udevice_id omap_ehci_dt_ids[] = {
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{ .compatible = "ti,ehci-omap" },
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{ }
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};
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U_BOOT_DRIVER(usb_omap_ehci) = {
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.name = "omap-ehci",
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.id = UCLASS_USB,
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.of_match = omap_ehci_dt_ids,
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.probe = omap_ehci_probe,
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.of_to_plat = ehci_usb_of_to_plat,
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.plat_auto = sizeof(struct usb_plat),
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.priv_auto = sizeof(struct ehci_omap_priv_data),
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.remove = ehci_deregister,
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.ops = &ehci_usb_ops,
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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