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https://github.com/AsahiLinux/u-boot
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90bb5c08c8
This code is not enabled anywhere, drop it. Signed-off-by: Tom Rini <trini@konsulko.com>
293 lines
7.5 KiB
C
293 lines
7.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Freescale i.MX28 USB Host driver
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <errno.h>
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#include <linux/delay.h>
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#include <dm.h>
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#include <power/regulator.h>
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#include "ehci.h"
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/* This DIGCTL register ungates clock to USB */
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#define HW_DIGCTL_CTRL 0x8001c000
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#define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2)
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#define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16)
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struct ehci_mxs_port {
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uint32_t usb_regs;
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struct mxs_usbphy_regs *phy_regs;
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struct mxs_register_32 *pll;
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uint32_t pll_en_bits;
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uint32_t pll_dis_bits;
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uint32_t gate_bits;
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};
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static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable)
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{
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struct mxs_register_32 *digctl_ctrl =
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(struct mxs_register_32 *)HW_DIGCTL_CTRL;
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int pll_offset, dig_offset;
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if (enable) {
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pll_offset = offsetof(struct mxs_register_32, reg_set);
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dig_offset = offsetof(struct mxs_register_32, reg_clr);
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writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
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writel(port->pll_en_bits, (u32)port->pll + pll_offset);
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} else {
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pll_offset = offsetof(struct mxs_register_32, reg_clr);
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dig_offset = offsetof(struct mxs_register_32, reg_set);
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writel(port->pll_dis_bits, (u32)port->pll + pll_offset);
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writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
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}
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return 0;
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}
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static int __ehci_hcd_init(struct ehci_mxs_port *port, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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u32 usb_base, cap_base;
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int ret;
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/* Reset the PHY block */
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writel(USBPHY_CTRL_SFTRST, &port->phy_regs->hw_usbphy_ctrl_set);
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udelay(10);
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writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE,
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&port->phy_regs->hw_usbphy_ctrl_clr);
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/* Enable USB clock */
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ret = ehci_mxs_toggle_clock(port, 1);
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if (ret)
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return ret;
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/* Start USB PHY */
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writel(0, &port->phy_regs->hw_usbphy_pwd);
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/* Enable UTMI+ Level 2 and Level 3 compatibility */
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writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1,
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&port->phy_regs->hw_usbphy_ctrl_set);
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usb_base = port->usb_regs + 0x100;
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*hccr = (struct ehci_hccr *)usb_base;
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cap_base = ehci_readl(&(*hccr)->cr_capbase);
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*hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
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return 0;
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}
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static int __ehci_hcd_stop(struct ehci_mxs_port *port)
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{
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u32 usb_base, cap_base, tmp;
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struct ehci_hccr *hccr;
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struct ehci_hcor *hcor;
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/* Stop the USB port */
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usb_base = port->usb_regs + 0x100;
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hccr = (struct ehci_hccr *)usb_base;
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cap_base = ehci_readl(&hccr->cr_capbase);
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hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
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tmp = ehci_readl(&hcor->or_usbcmd);
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tmp &= ~CMD_RUN;
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ehci_writel(&hcor->or_usbcmd, tmp);
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/* Disable the PHY */
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tmp = USBPHY_PWD_RXPWDRX | USBPHY_PWD_RXPWDDIFF |
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USBPHY_PWD_RXPWD1PT1 | USBPHY_PWD_RXPWDENV |
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USBPHY_PWD_TXPWDV2I | USBPHY_PWD_TXPWDIBIAS |
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USBPHY_PWD_TXPWDFS;
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writel(tmp, &port->phy_regs->hw_usbphy_pwd);
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/* Disable USB clock */
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return ehci_mxs_toggle_clock(port, 0);
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}
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struct ehci_mxs_priv_data {
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struct ehci_ctrl ctrl;
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struct usb_ehci *ehci;
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struct udevice *vbus_supply;
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struct ehci_mxs_port port;
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enum usb_init_type init_type;
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};
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/*
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* Below defines correspond to imx28 clk Linux (v5.15.y)
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* clock driver to provide proper offset for PHY[01]
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* devices.
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*/
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#define CLK_USB_PHY0 62
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#define CLK_USB_PHY1 63
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#define PLL0CTRL0(base) ((base) + 0x0000)
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#define PLL1CTRL0(base) ((base) + 0x0020)
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static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
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{
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struct ehci_mxs_priv_data *priv = dev_get_priv(dev);
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struct usb_plat *plat = dev_get_plat(dev);
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struct ehci_mxs_port *port = &priv->port;
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u32 phandle, phy_reg, clk_reg, clk_id;
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ofnode phy_node, clk_node;
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const char *mode;
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int ret;
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mode = ofnode_read_string(dev->node_, "dr_mode");
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if (mode) {
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if (strcmp(mode, "peripheral") == 0)
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plat->init_type = USB_INIT_DEVICE;
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else if (strcmp(mode, "host") == 0)
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plat->init_type = USB_INIT_HOST;
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else
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return -EINVAL;
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}
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/* Read base address of the USB IP block */
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ret = ofnode_read_u32(dev->node_, "reg", &port->usb_regs);
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if (ret)
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return ret;
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/* Read base address of the USB PHY IP block */
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ret = ofnode_read_u32(dev->node_, "fsl,usbphy", &phandle);
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if (ret)
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return ret;
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phy_node = ofnode_get_by_phandle(phandle);
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if (!ofnode_valid(phy_node))
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return -ENODEV;
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ret = ofnode_read_u32(phy_node, "reg", &phy_reg);
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if (ret)
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return ret;
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port->phy_regs = (struct mxs_usbphy_regs *)phy_reg;
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/* Read base address of the CLK IP block and proper ID */
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ret = ofnode_read_u32_index(phy_node, "clocks", 0, &phandle);
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if (ret)
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return ret;
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ret = ofnode_read_u32_index(phy_node, "clocks", 1, &clk_id);
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if (ret)
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return ret;
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clk_node = ofnode_get_by_phandle(phandle);
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if (!ofnode_valid(clk_node))
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return -ENODEV;
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ret = ofnode_read_u32(clk_node, "reg", &clk_reg);
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if (ret)
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return ret;
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port->pll = (struct mxs_register_32 *)clk_reg;
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/* Provide proper offset for USB PHY clocks */
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if (clk_id == CLK_USB_PHY0)
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port->pll = PLL0CTRL0(port->pll);
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if (clk_id == CLK_USB_PHY1)
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port->pll = PLL1CTRL0(port->pll);
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debug("%s: pll_reg: 0x%p clk_id: %d\n", __func__, port->pll, clk_id);
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/*
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* On the imx28 the values provided by CLKCTRL_PLL0* defines to are the
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* same as ones for CLKCTRL_PLL1*. As a result the former can be used
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* for both ports - i.e. (usb[01]).
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*/
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port->pll_en_bits = CLKCTRL_PLL0CTRL0_EN_USB_CLKS |
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CLKCTRL_PLL0CTRL0_POWER;
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port->pll_dis_bits = CLKCTRL_PLL0CTRL0_EN_USB_CLKS;
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port->gate_bits = HW_DIGCTL_CTRL_USB0_CLKGATE;
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return 0;
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}
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static int ehci_usb_probe(struct udevice *dev)
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{
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struct usb_plat *plat = dev_get_plat(dev);
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struct usb_ehci *ehci = dev_read_addr_ptr(dev);
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struct ehci_mxs_priv_data *priv = dev_get_priv(dev);
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struct ehci_mxs_port *port = &priv->port;
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enum usb_init_type type = plat->init_type;
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struct ehci_hccr *hccr;
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struct ehci_hcor *hcor;
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int ret;
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priv->ehci = ehci;
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priv->init_type = type;
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debug("%s: USB type: %s reg: 0x%x phy_reg 0x%p\n", __func__,
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type == USB_INIT_HOST ? "HOST" : "DEVICE", port->usb_regs,
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(uint32_t *)port->phy_regs);
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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ret = device_get_supply_regulator(dev, "vbus-supply",
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&priv->vbus_supply);
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if (ret)
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debug("%s: No vbus supply\n", dev->name);
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if (!ret && priv->vbus_supply) {
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ret = regulator_set_enable(priv->vbus_supply,
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(type == USB_INIT_DEVICE) ?
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false : true);
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if (ret) {
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puts("Error enabling VBUS supply\n");
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return ret;
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}
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}
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#endif
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ret = __ehci_hcd_init(port, type, &hccr, &hcor);
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if (ret)
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return ret;
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mdelay(10);
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return ehci_register(dev, hccr, hcor, NULL, 0, priv->init_type);
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}
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static int ehci_usb_remove(struct udevice *dev)
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{
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struct ehci_mxs_priv_data *priv = dev_get_priv(dev);
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struct ehci_mxs_port *port = &priv->port;
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int ret;
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ret = ehci_deregister(dev);
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if (ret)
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return ret;
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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if (priv->vbus_supply) {
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ret = regulator_set_enable(priv->vbus_supply, false);
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if (ret) {
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puts("Error disabling VBUS supply\n");
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return ret;
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}
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}
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#endif
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return __ehci_hcd_stop(port);
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}
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static const struct udevice_id mxs_usb_ids[] = {
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{ .compatible = "fsl,imx28-usb" },
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{ }
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};
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U_BOOT_DRIVER(usb_mxs) = {
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.name = "ehci_mxs",
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.id = UCLASS_USB,
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.of_match = mxs_usb_ids,
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.of_to_plat = ehci_usb_ofdata_to_platdata,
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.probe = ehci_usb_probe,
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.remove = ehci_usb_remove,
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.ops = &ehci_usb_ops,
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.plat_auto = sizeof(struct usb_plat),
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.priv_auto = sizeof(struct ehci_mxs_priv_data),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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