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https://github.com/AsahiLinux/u-boot
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87c692cbc1
Remove busy looping during watchdog reset.
Each polling of W_PEND_WTGR bit ("finish posted
write") after watchdog reset takes 120-140us
on BeagleBone Black board. Current U-Boot code
has watchdog resets in random places and often
there is situation when watchdog is reset
few times in a row in nested functions.
This adds extra delays and slows the whole system.
Instead of polling W_PEND_WTGR bit, we skip
watchdog reset if the bit is set. Anyway, watchdog
is in the middle of reset *right now*, so we can
just return.
This noticeably increases performance of the
system. Below are some measurements on BBB:
- DFU upload over USB 15% faster
- fastboot image upload 3x times faster
- USB ep0 transfers with 4k packets 20% faster
Signed-off-by: Ruslan Bilovol <ruslan.bilovol@gmail.com>
Tested-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Alex Kiernan <alex.kiernan@gmail.com>
137 lines
3.4 KiB
C
137 lines
3.4 KiB
C
/*
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* omap_wdt.c
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*
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* (C) Copyright 2013
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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* Based on:
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*
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* Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
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*
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* commit 2d991a164a61858012651e13c59521975504e260
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* Author: Bill Pemberton <wfp5p@virginia.edu>
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* Date: Mon Nov 19 13:21:41 2012 -0500
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*
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* watchdog: remove use of __devinit
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*
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* CONFIG_HOTPLUG is going away as an option so __devinit is no longer
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* needed.
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*
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* Author: MontaVista Software, Inc.
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* <gdavis@mvista.com> or <source@mvista.com>
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*
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* History:
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*
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* 20030527: George G. Davis <gdavis@mvista.com>
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* Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
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* (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
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* Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
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*
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* Copyright (c) 2004 Texas Instruments.
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* 1. Modified to support OMAP1610 32-KHz watchdog timer
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* 2. Ported to 2.6 kernel
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*
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* Copyright (c) 2005 David Brownell
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* Use the driver model and standard identifiers; handle bigger timeouts.
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/arch/cpu.h>
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/* Hardware timeout in seconds */
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#define WDT_HW_TIMEOUT 60
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static unsigned int wdt_trgr_pattern = 0x1234;
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void hw_watchdog_reset(void)
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{
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struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
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/*
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* Somebody just triggered watchdog reset and write to WTGR register
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* is in progress. It is resetting right now, no need to trigger it
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* again
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*/
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if ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR)
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return;
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wdt_trgr_pattern = ~wdt_trgr_pattern;
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writel(wdt_trgr_pattern, &wdt->wdtwtgr);
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/*
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* Don't wait for posted write to complete, i.e. don't check
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* WDT_WWPS_PEND_WTGR bit in WWPS register. There is no writes to
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* WTGR register outside of this func, and if entering it
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* we see WDT_WWPS_PEND_WTGR bit set, it means watchdog reset
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* was just triggered. This prevents us from wasting time in busy
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* polling of WDT_WWPS_PEND_WTGR bit.
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*/
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}
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static int omap_wdt_set_timeout(unsigned int timeout)
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{
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struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
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u32 pre_margin = GET_WLDR_VAL(timeout);
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/* just count up at 32 KHz */
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while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR)
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;
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writel(pre_margin, &wdt->wdtwldr);
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while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR)
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;
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return 0;
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}
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void hw_watchdog_disable(void)
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{
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struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
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/*
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* Disable watchdog
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*/
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writel(0xAAAA, &wdt->wdtwspr);
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while (readl(&wdt->wdtwwps) != 0x0)
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;
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writel(0x5555, &wdt->wdtwspr);
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while (readl(&wdt->wdtwwps) != 0x0)
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;
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}
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void hw_watchdog_init(void)
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{
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struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
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/*
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* Make sure the watchdog is disabled. This is unfortunately required
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* because writing to various registers with the watchdog running has no
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* effect.
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*/
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hw_watchdog_disable();
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/* initialize prescaler */
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while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
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;
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writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &wdt->wdtwclr);
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while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
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;
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omap_wdt_set_timeout(WDT_HW_TIMEOUT);
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/* Sequence to enable the watchdog */
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writel(0xBBBB, &wdt->wdtwspr);
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while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
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;
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writel(0x4444, &wdt->wdtwspr);
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while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
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;
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}
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