mirror of
https://github.com/AsahiLinux/u-boot
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fa760c3240
Perform a simple rename of CONFIG_FEC_MXC_PHYADDR to CFG_FEC_MXC_PHYADDR Signed-off-by: Tom Rini <trini@konsulko.com>
79 lines
2.2 KiB
C
79 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*/
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#ifndef __IMX8M_PICOPI_H
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#define __IMX8M_PICOPI_H
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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#ifdef CONFIG_SPL_BUILD
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/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
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#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
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/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
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#define CONFIG_MALLOC_F_ADDR 0x182000
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/* For RAW image gives a error info not panic */
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#endif
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/* ENET Config */
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/* ENET1 */
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#if defined(CONFIG_CMD_NET)
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#define CFG_FEC_MXC_PHYADDR 1
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#endif
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/* Initial environment variables */
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#define CFG_EXTRA_ENV_SETTINGS \
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"script=boot.scr\0" \
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"image=Image\0" \
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"console=ttymxc0,115200\0" \
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"fdt_addr=0x43000000\0" \
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"fdt_high=0xffffffffffffffff\0" \
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"fdt_file=imx8mq-pico-pi.dtb\0" \
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"initrd_addr=0x43800000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
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"mmcpart=1\0" \
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
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"loadbootscript=" \
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"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; source\0" \
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"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
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"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"echo wait for boot; " \
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"fi;\0" \
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"netargs=setenv bootargs console=${console} " \
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"root=/dev/nfs " \
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"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
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"netboot=echo Booting from net ...; " \
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"run netargs; " \
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"if test ${ip_dyn} = yes; then " \
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"setenv get_cmd dhcp; " \
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"else " \
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"setenv get_cmd tftp; " \
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"fi; " \
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"${get_cmd} ${loadaddr} ${image}; " \
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"booti; "
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/* Link Definitions */
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#define CFG_SYS_INIT_RAM_ADDR 0x40000000
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#define CFG_SYS_INIT_RAM_SIZE 0x80000
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#define CFG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */
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#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
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#define CFG_SYS_FSL_USDHC_NUM 2
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#define CFG_SYS_FSL_ESDHC_ADDR 0
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#endif
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