mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-06 05:04:26 +00:00
90526e9fba
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
432 lines
10 KiB
C
432 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* board.c
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*
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* Board functions for Birdland Audio BAV335x Network Processor
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*
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* Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
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*/
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#include <common.h>
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#include <env.h>
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#include <errno.h>
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#include <init.h>
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#include <net.h>
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#include <serial.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <power/tps65217.h>
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#include <power/tps65910.h>
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#include <env_internal.h>
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#include <watchdog.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* GPIO that controls power to DDR on EVM-SK */
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#define GPIO_DDR_VTT_EN 7
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static __maybe_unused struct ctrl_dev *cdev =
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(struct ctrl_dev *)CTRL_DEVICE_BASE;
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/*
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* Read header information from EEPROM into global structure.
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*/
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static int read_eeprom(struct board_eeconfig *header)
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{
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/* Check if baseboard eeprom is available */
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if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR))
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return -ENODEV;
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/* read the eeprom using i2c */
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
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sizeof(struct board_eeconfig)))
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return -EIO;
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if (header->magic != BOARD_MAGIC) {
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/* read the i2c eeprom again using only a 1 byte address */
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
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sizeof(struct board_eeconfig)))
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return -EIO;
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if (header->magic != BOARD_MAGIC)
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return -EINVAL;
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}
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return 0;
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}
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enum board_type get_board_type(bool debug)
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{
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int ecode;
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struct board_eeconfig header;
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ecode = read_eeprom(&header);
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if (ecode == 0) {
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if (header.version[1] == 'A') {
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if (debug)
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puts("=== Detected Board model BAV335x Rev.A");
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return BAV335A;
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} else if (header.version[1] == 'B') {
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if (debug)
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puts("=== Detected Board model BAV335x Rev.B");
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return BAV335B;
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} else if (debug) {
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puts("### Un-known board model in serial-EE\n");
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}
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} else if (debug) {
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switch (ecode) {
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case -ENODEV:
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puts("### Board doesn't have a serial-EE\n");
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break;
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case -EINVAL:
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puts("### Board serial-EE signature is incorrect.\n");
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break;
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default:
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puts("### IO Error reading serial-EE.\n");
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break;
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}
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}
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#if (CONFIG_BAV_VERSION == 1)
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if (debug)
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puts("### Selecting BAV335A as per config\n");
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return BAV335A;
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#elif (CONFIG_BAV_VERSION == 2)
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if (debug)
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puts("### Selecting BAV335B as per config\n");
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return BAV335B;
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#endif
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#if (NOT_DEFINED == 2)
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#error "SHOULD NEVER DISPLAY THIS"
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#endif
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if (debug)
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puts("### Defaulting to model BAV335x Rev.B\n");
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return BAV335B;
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}
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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static const struct ddr_data ddr3_bav335x_data = {
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.datardsratio0 = MT41K256M16HA125E_RD_DQS,
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_bav335x_cmd_ctrl_data = {
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.cmd0csratio = MT41K256M16HA125E_RATIO,
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd1csratio = MT41K256M16HA125E_RATIO,
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd2csratio = MT41K256M16HA125E_RATIO,
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_bav335x_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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};
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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if (serial_tstc() && serial_getc() == 'c')
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return 1;
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#ifdef CONFIG_SPL_ENV_SUPPORT
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env_init();
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env_load();
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if (env_get_yesno("boot_os") != 1)
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return 1;
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#endif
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return 0;
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}
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#endif
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#define OSC (V_OSCK/1000000)
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const struct dpll_params dpll_ddr = {
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266, OSC-1, 1, -1, -1, -1, -1};
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const struct dpll_params dpll_ddr_evm_sk = {
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303, OSC-1, 1, -1, -1, -1, -1};
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const struct dpll_params dpll_ddr_bone_black = {
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400, OSC-1, 1, -1, -1, -1, -1};
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void am33xx_spl_board_init(void)
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{
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/* debug print detect status */
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(void)get_board_type(true);
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/* Get the frequency */
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/* dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); */
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dpll_mpu_opp100.m = MPUPLL_M_1000;
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if (i2c_probe(TPS65217_CHIP_PM))
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return;
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/* Set the USB Current Limit */
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if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
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TPS65217_USB_INPUT_CUR_LIMIT_1800MA,
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TPS65217_USB_INPUT_CUR_LIMIT_MASK))
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puts("! tps65217_reg_write: could not set USB limit\n");
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/* Set the Core Voltage (DCDC3) to 1.125V */
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if (tps65217_voltage_update(TPS65217_DEFDCDC3,
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TPS65217_DCDC_VOLT_SEL_1125MV)) {
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puts("! tps65217_reg_write: could not set Core Voltage\n");
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return;
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}
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/* Set CORE Frequencies to OPP100 */
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do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
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/* Set the MPU Voltage (DCDC2) */
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if (tps65217_voltage_update(TPS65217_DEFDCDC2,
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TPS65217_DCDC_VOLT_SEL_1325MV)) {
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puts("! tps65217_reg_write: could not set MPU Voltage\n");
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return;
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}
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/*
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* Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
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* Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
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*/
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if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1,
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TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK))
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puts("! tps65217_reg_write: could not set LDO3\n");
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if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2,
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TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK))
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puts("! tps65217_reg_write: could not set LDO4\n");
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/* Set MPU Frequency to what we detected now that voltages are set */
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do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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enable_i2c0_pin_mux();
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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return &dpll_ddr_bone_black;
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}
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void set_uart_mux_conf(void)
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{
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#if CONFIG_CONS_INDEX == 1
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enable_uart0_pin_mux();
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#elif CONFIG_CONS_INDEX == 2
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enable_uart1_pin_mux();
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#elif CONFIG_CONS_INDEX == 3
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enable_uart2_pin_mux();
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#elif CONFIG_CONS_INDEX == 4
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enable_uart3_pin_mux();
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#elif CONFIG_CONS_INDEX == 5
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enable_uart4_pin_mux();
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#elif CONFIG_CONS_INDEX == 6
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enable_uart5_pin_mux();
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#endif
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}
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void set_mux_conf_regs(void)
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{
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enum board_type board;
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board = get_board_type(false);
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enable_board_pin_mux(board);
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}
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const struct ctrl_ioregs ioregs_bonelt = {
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.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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};
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void sdram_init(void)
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{
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config_ddr(400, &ioregs_bonelt,
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&ddr3_bav335x_data,
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&ddr3_bav335x_cmd_ctrl_data,
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&ddr3_bav335x_emif_reg_data, 0);
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}
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#endif
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/*
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* Basic board specific setup. Pinmux has been handled already.
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*/
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int board_init(void)
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{
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#if defined(CONFIG_HW_WATCHDOG)
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hw_watchdog_init();
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#endif
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
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gpmc_init();
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#endif
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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env_set("board_name", "BAV335xB");
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env_set("board_rev", "B"); /* Fix me, but why bother.. */
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#endif
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return 0;
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}
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#endif
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_addr = 0,
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},
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{
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.slave_reg_ofs = 0x308,
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.sliver_reg_ofs = 0xdc0,
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.phy_addr = 1,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x800,
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.slaves = 1,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.bd_ram_ofs = 0x2000,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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#endif
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/*
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* This function will:
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* Perform fixups to the PHY present on certain boards. We only need this
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* function in:
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* - SPL with either CPSW or USB ethernet support
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* - Full U-Boot, with either CPSW or USB ethernet
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* Build in only these cases to avoid warnings about unused variables
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* when we build an SPL that has neither option but full U-Boot will.
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*/
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#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) &&\
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defined(CONFIG_SPL_BUILD)) || \
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((defined(CONFIG_DRIVER_TI_CPSW) || \
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defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
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!defined(CONFIG_SPL_BUILD))
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int board_eth_init(bd_t *bis)
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{
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int ecode, rv, n;
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uint8_t mac_addr[6];
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struct board_eeconfig header;
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__maybe_unused enum board_type board;
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/* Default manufacturing address; used when no EE or invalid */
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n = 0;
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mac_addr[0] = 0;
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mac_addr[1] = 0x20;
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mac_addr[2] = 0x18;
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mac_addr[3] = 0x1C;
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mac_addr[4] = 0x00;
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mac_addr[5] = 0x01;
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ecode = read_eeprom(&header);
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/* if we have a valid EE, get mac address from there */
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if ((ecode == 0) &&
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is_valid_ethaddr((const u8 *)&header.mac_addr[0][0])) {
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memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6);
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}
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
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if (!env_get("ethaddr")) {
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printf("<ethaddr> not set. Validating first E-fuse MAC\n");
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if (is_valid_ethaddr(mac_addr))
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eth_env_set_enetaddr("ethaddr", mac_addr);
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}
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#ifdef CONFIG_DRIVER_TI_CPSW
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board = get_board_type(false);
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/* Rev.A uses 10/100 PHY in mii mode */
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if (board == BAV335A) {
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writel(MII_MODE_ENABLE, &cdev->miisel);
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cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
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cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
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}
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/* Rev.B (default) uses GB PHY in rmii mode */
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else {
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writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
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cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if
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= PHY_INTERFACE_MODE_RGMII;
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}
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rv = cpsw_register(&cpsw_data);
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if (rv < 0)
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printf("Error %d registering CPSW switch\n", rv);
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else
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n += rv;
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#endif
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#endif
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return n;
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}
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#endif
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