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https://github.com/AsahiLinux/u-boot
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76b3f195e9
ARM supported speeds and init value of core_pll for SDP1200 are programmed wrong as part for the device speed cleanups. Fixing it here. Thanks to "Vitaly Andrianov <vitalya@ti.com>" for bisecting this issue Fixes: c37ed9f11b61 ("ARM: keystone2: Fix dev and arm speed detection") Tested-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
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.. | ||
include/mach | ||
clock-k2e.c | ||
clock-k2hk.c | ||
clock-k2l.c | ||
clock.c | ||
cmd_clock.c | ||
cmd_ddr3.c | ||
cmd_mon.c | ||
config.mk | ||
ddr3.c | ||
init.c | ||
Kconfig | ||
keystone.c | ||
Makefile | ||
msmc.c | ||
psc.c |