mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-05 20:54:31 +00:00
fcc238baee
Now PLLs for DRAM controller are initialized in SPL, and the others in U-Boot proper. Setting up all of them in a single directory will be helpful when we want to share code between SPL and U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
32 lines
643 B
C
32 lines
643 B
C
/*
|
|
* Copyright (C) 2016 Socionext Inc.
|
|
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <linux/io.h>
|
|
|
|
#include "../init.h"
|
|
#include "../sc64-regs.h"
|
|
|
|
int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd)
|
|
{
|
|
u32 tmp;
|
|
|
|
/* deassert reset */
|
|
tmp = readl(SC_RSTCTRL7);
|
|
tmp |= SC_RSTCTRL7_UMC31 | SC_RSTCTRL7_UMC30;
|
|
writel(tmp, SC_RSTCTRL7);
|
|
|
|
/* provide clocks */
|
|
tmp = readl(SC_CLKCTRL4);
|
|
tmp |= SC_CLKCTRL4_PERI;
|
|
writel(tmp, SC_CLKCTRL4);
|
|
|
|
tmp = readl(SC_CLKCTRL7);
|
|
tmp |= SC_CLKCTRL7_UMC31 | SC_CLKCTRL7_UMC30;
|
|
writel(tmp, SC_CLKCTRL7);
|
|
|
|
return 0;
|
|
}
|