u-boot/arch/arm/mach-uniphier/clk/dpll-ld11.c
Masahiro Yamada c72f4d4c2e ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious
   SPL memory footprint)
 - Adjust CPLL/MPLL to the final tape-out frequency
 - Set the Cortex-A53 clock to the maximum frequency since it is
   running at 500MHz (SPLL/4) on startup

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-23 01:00:23 +09:00

16 lines
306 B
C

/*
* Copyright (C) 2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "../init.h"
#include "../sc64-regs.h"
#include "pll.h"
int uniphier_ld11_dpll_init(const struct uniphier_board_data *bd)
{
uniphier_ld20_sscpll_init(SC_DPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
return 0;
}