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3524d47c79
Clarify these clock data are constant. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
147 lines
3.3 KiB
C
147 lines
3.3 KiB
C
/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <clk-uclass.h>
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#include <dm/device.h>
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#include "clk-uniphier.h"
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static int uniphier_clk_enable(struct clk *clk)
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{
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struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
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const struct uniphier_clk_gate_data *gate = priv->socdata->gate;
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unsigned int nr_gate = priv->socdata->nr_gate;
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void __iomem *reg;
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u32 mask, data, tmp;
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int i;
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for (i = 0; i < nr_gate; i++) {
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if (gate[i].index != clk->id)
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continue;
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reg = priv->base + gate[i].reg;
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mask = gate[i].mask;
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data = gate[i].data & mask;
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tmp = readl(reg);
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tmp &= ~mask;
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tmp |= data & mask;
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debug("%s: %p: %08x\n", __func__, reg, tmp);
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writel(tmp, reg);
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}
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return 0;
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}
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static ulong uniphier_clk_get_rate(struct clk *clk)
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{
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struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
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const struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
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unsigned int nr_rdata = priv->socdata->nr_rate;
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void __iomem *reg;
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u32 mask, data;
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ulong matched_rate = 0;
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int i;
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for (i = 0; i < nr_rdata; i++) {
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if (rdata[i].index != clk->id)
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continue;
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if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)
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return rdata[i].rate;
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reg = priv->base + rdata[i].reg;
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mask = rdata[i].mask;
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data = rdata[i].data & mask;
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if ((readl(reg) & mask) == data) {
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if (matched_rate && rdata[i].rate != matched_rate) {
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printf("failed to get clk rate for insane register values\n");
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return -EINVAL;
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}
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matched_rate = rdata[i].rate;
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}
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}
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debug("%s: rate = %lu\n", __func__, matched_rate);
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return matched_rate;
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}
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static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate)
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{
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struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
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const struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
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unsigned int nr_rdata = priv->socdata->nr_rate;
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void __iomem *reg;
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u32 mask, data, tmp;
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ulong best_rate = 0;
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int i;
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/* first, decide the best match rate */
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for (i = 0; i < nr_rdata; i++) {
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if (rdata[i].index != clk->id)
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continue;
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if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)
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return 0;
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if (rdata[i].rate > best_rate && rdata[i].rate <= rate)
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best_rate = rdata[i].rate;
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}
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if (!best_rate)
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return -ENODEV;
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debug("%s: requested rate = %lu, set rate = %lu\n", __func__,
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rate, best_rate);
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/* second, really set registers */
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for (i = 0; i < nr_rdata; i++) {
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if (rdata[i].index != clk->id || rdata[i].rate != best_rate)
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continue;
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reg = priv->base + rdata[i].reg;
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mask = rdata[i].mask;
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data = rdata[i].data & mask;
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tmp = readl(reg);
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tmp &= ~mask;
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tmp |= data;
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debug("%s: %p: %08x\n", __func__, reg, tmp);
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writel(tmp, reg);
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}
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return best_rate;
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}
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const struct clk_ops uniphier_clk_ops = {
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.enable = uniphier_clk_enable,
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.get_rate = uniphier_clk_get_rate,
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.set_rate = uniphier_clk_set_rate,
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};
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int uniphier_clk_probe(struct udevice *dev)
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{
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struct uniphier_clk_priv *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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addr = dev_get_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->base = devm_ioremap(dev, addr, SZ_4K);
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if (!priv->base)
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return -ENOMEM;
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priv->socdata = (void *)dev_get_driver_data(dev);
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return 0;
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}
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