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486f25c727
I2C muxes that have the slave devices with same address are falling into the below problem. VCK190 system controller (SC) - zynqmp-e-a2197-00-revA.dts I2C1 (0xff030000) -> Mux1 (@0x74) -> Channel 3 -> 0x50 I2C1 (0xff030000) -> Mux2 (@0x75) -> Channel 0 -> 0x50 1. SC accesses I2C1 - Mux1 (0x74) - Channel 3 and then 2. SC accesses I2C1 - Mux2 (0x75) - Channel 0. Now it results in 2 slave devices with same address (0x50) on the I2C bus, making the communication un-reliable. When ' i2c-mux-idle-disconnect' is in DT, after '1', the Mux channel output is disconnected, making none of the channels available to the I2C1. So, there is no question of having the same addressed slave (0x50) present on the bus when we are doing '2'. Same pattern is seen in below two boards also. ZCU208 - zynqmp-zcu208-revA.dts ZCU216 - zynqmp-zcu216-revA.dts Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
598 lines
16 KiB
Text
598 lines
16 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx Versal a2197 RevA System Controller
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*
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* (C) Copyright 2019 - 2021, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */
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compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
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"xlnx,zynqmp-a2197", "xlnx,zynqmp";
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aliases {
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ethernet0 = &gem0;
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gpio0 = &gpio;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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mmc0 = &sdhci1;
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rtc0 = &rtc;
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serial0 = &uart0;
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serial1 = &dcc;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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xlnx,eeprom = <&eeprom>;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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ina226-vccint {
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compatible = "iio-hwmon";
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io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
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};
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ina226-vcc-soc {
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compatible = "iio-hwmon";
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io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;
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};
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ina226-vcc-pmc {
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compatible = "iio-hwmon";
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io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;
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};
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ina226-vcc-ram {
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compatible = "iio-hwmon";
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io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
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};
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ina226-vcc-pslp {
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compatible = "iio-hwmon";
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io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;
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};
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ina226-vcc-psfp {
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compatible = "iio-hwmon";
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io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;
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};
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ina226-vccaux {
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compatible = "iio-hwmon";
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io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;
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};
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ina226-vccaux-pmc {
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compatible = "iio-hwmon";
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io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;
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};
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ina226-vcco-500 {
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compatible = "iio-hwmon";
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io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;
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};
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ina226-vcco-501 {
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compatible = "iio-hwmon";
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io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;
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};
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ina226-vcco-502 {
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compatible = "iio-hwmon";
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io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;
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};
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ina226-vcco-503 {
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compatible = "iio-hwmon";
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io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;
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};
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ina226-vcc-1v8 {
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compatible = "iio-hwmon";
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io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;
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};
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ina226-vcc-3v3 {
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compatible = "iio-hwmon";
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io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;
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};
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ina226-vcc-1v2-ddr4 {
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compatible = "iio-hwmon";
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io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;
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};
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ina226-vcc-1v1-lp4 {
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compatible = "iio-hwmon";
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io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
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};
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ina226-vadj-fmc {
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compatible = "iio-hwmon";
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io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
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};
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ina226-mgtyavcc {
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compatible = "iio-hwmon";
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io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;
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};
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ina226-mgtyavtt {
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compatible = "iio-hwmon";
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io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;
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};
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ina226-mgtyvccaux {
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compatible = "iio-hwmon";
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io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;
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};
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};
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&uart0 { /* uart0 MIO38-39 */
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status = "okay";
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u-boot,dm-pre-reloc;
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};
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&sdhci1 { /* sd1 MIO45-51 cd in place */
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status = "okay";
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no-1-8-v;
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disable-wp;
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xlnx,mio-bank = <1>;
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};
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&gem0 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "sgmii";
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is-internal-pcspma;
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phy0: ethernet-phy@0 { /* u131 M88E1512 */
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reg = <0>;
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};
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};
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&gpio {
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status = "okay";
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gpio-line-names = "", "", "", "", "", /* 0 - 4 */
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"", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
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"DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */
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"", "", "", "", "", /* 15 - 19 */
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"", "", "", "", "", /* 20 - 24 */
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"", "", "", "", "", /* 25 - 29 */
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"", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
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"LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
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"", "", "ETH_RESET_B", "", "", /* 40 - 44 */
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"SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
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"SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */
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"", "", "", "", "", /* 55 - 59 */
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"", "", "", "", "", /* 60 - 64 */
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"", "", "", "", "", /* 65 - 69 */
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"", "", "", "", "", /* 70 - 74 */
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"", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
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"SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
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"SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */
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"SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
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"SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
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"SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
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"", "", "", "", "", /* 100 - 104 */
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"", "", "", "", "", /* 105 - 109 */
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"", "", "", "", "", /* 110 - 114 */
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"", "", "", "", "", /* 115 - 119 */
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"", "", "", "", "", /* 120 - 124 */
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"", "", "", "", "", /* 125 - 129 */
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"PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */
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"", "", "", "", "", /* 135 - 139 */
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"PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
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"MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
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"", "", "", "", "", /* 150 - 154 */
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"", "", "", "", "", /* 155 - 159 */
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"", "", "", "", "", /* 160 - 164 */
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"", "", "", "", "", /* 165 - 169 */
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"", "", "", ""; /* 170 - 174 */
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};
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&i2c0 { /* MIO 34-35 - can't stay here */
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status = "okay";
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clock-frequency = <400000>;
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i2c-mux@74 { /* u33 */
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x74>;
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/* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
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i2c@0 { /* PMBUS */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/* u152 IR35215 0x16/0x46 vcc_soc */
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/* u179 ir38164 0x19/0x49 vcco_500 */
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/* u181 ir38164 0x1a/0x4a vcco_501 */
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/* u183 ir38164 0x1b/0x4b vcco_502 */
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/* u185 ir38164 0x1e/0x4e vadj_fmc */
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/* u187 ir38164 0x1F/0x4f mgtyavcc */
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/* u189 ir38164 0x20/0x50 mgtyavtt */
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/* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */
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/* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */
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irps5401_47: irps5401@47 { /* IRPS5401 - u160 */
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compatible = "infineon,irps5401";
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reg = <0x47>; /* pmbus / i2c 0x17 */
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};
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irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */
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compatible = "infineon,irps5401";
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reg = <0x4c>; /* pmbus / i2c 0x1c */
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};
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irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */
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compatible = "infineon,irps5401";
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reg = <0x4d>; /* pmbus / i2c 0x1d */
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};
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};
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i2c@1 { /* PMBUS1_INA226 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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/* FIXME check alerts coming to SC */
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vccint: ina226@40 { /* u65 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vccint";
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reg = <0x40>;
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shunt-resistor = <500>; /* R440 */
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/* 0.80V @ 32A 1 of 6 Phases*/
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};
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vcc_soc: ina226@41 { /* u161 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcc-soc";
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reg = <0x41>;
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shunt-resistor = <500>; /* R1702 */
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/* 0.80V @ 18A */
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};
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vcc_pmc: ina226@42 { /* u163 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcc-pmc";
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reg = <0x42>;
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shunt-resistor = <5000>; /* R1214 */
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/* 0.78V @ 500mA */
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};
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vcc_ram: ina226@43 { /* u162 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcc-ram";
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reg = <0x43>;
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shunt-resistor = <5000>; /* r1221 */
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/* 0.78V @ 4A */
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};
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vcc_pslp: ina226@44 { /* u165 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcc-pslp";
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reg = <0x44>;
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shunt-resistor = <5000>; /* R1216 */
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/* 0.78V @ 1A */
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};
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vcc_psfp: ina226@45 { /* u164 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcc-psfp";
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reg = <0x45>;
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shunt-resistor = <5000>; /* R1219 */
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/* 0.78V @ 2A */
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};
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};
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i2c@2 { /* PCIE_CLK */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */
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#clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
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compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
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reg = <0xd8>;
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/* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
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/* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
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};
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};
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i2c@3 { /* PMBUS2_INA226 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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/* FIXME check alerts coming to SC */
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vccaux: ina226@40 { /* u166 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vccaux";
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reg = <0x40>;
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shunt-resistor = <5000>; /* R382 */
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/* 1.5V @ 3A */
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};
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vccaux_pmc: ina226@41 { /* u168 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vccaux-pmc";
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reg = <0x41>;
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shunt-resistor = <5000>; /* R1246 */
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/* 1.5V @ 500mA */
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};
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vcco_500: ina226@42 { /* u178 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcco-500";
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reg = <0x42>;
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shunt-resistor = <2000>; /* R1300 */
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/* 3.3V @ 5A */
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};
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vcco_501: ina226@43 { /* u180 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcco-501";
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reg = <0x43>;
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shunt-resistor = <2000>; /* R1313 */
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/* 3.3V @ 5A */
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};
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vcco_502: ina226@44 { /* u182 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcco-502";
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reg = <0x44>;
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shunt-resistor = <2000>; /* R1330 */
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/* 3.3V @ 5A */
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};
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vcco_503: ina226@45 { /* u172 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcco-503";
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reg = <0x45>;
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shunt-resistor = <5000>; /* R1229 */
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/* 1.8V @ 2A */
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};
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vcc_1v8: ina226@46 { /* u173 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcc-1v8";
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reg = <0x46>;
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shunt-resistor = <5000>; /* R400 */
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/* 1.8V @ 6A */
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};
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vcc_3v3: ina226@47 { /* u174 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcc-3v3";
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reg = <0x47>;
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shunt-resistor = <5000>; /* R1232 */
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/* 3.3V @ 500mA */
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};
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vcc_1v2_ddr4: ina226@48 { /* u176 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcc-1v2-ddr4";
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reg = <0x48>;
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shunt-resistor = <5000>; /* R1275 */
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/* 1.2V @ 4A */
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};
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vcc1v1_lp4: ina226@49 { /* u177 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcc1v1-lp4";
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reg = <0x49>;
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shunt-resistor = <5000>; /* R1286 */
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/* 1.1V @ 4A */
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};
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vadj_fmc: ina226@4a { /* u184 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vadj-fmc";
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reg = <0x4a>;
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shunt-resistor = <2000>; /* R1350 */
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/* 1.5V @ 10A */
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};
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mgtyavcc: ina226@4b { /* u186 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-mgtyavcc";
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reg = <0x4b>;
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shunt-resistor = <2000>; /* R1367 */
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/* 0.88V @ 6A */
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};
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mgtyavtt: ina226@4c { /* u188 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-mgtyavtt";
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reg = <0x4c>;
|
|
shunt-resistor = <2000>; /* R1384 */
|
|
/* 1.2V @ 10A */
|
|
};
|
|
mgtyvccaux: ina226@4d { /* u234 */
|
|
compatible = "ti,ina226";
|
|
#io-channel-cells = <1>;
|
|
label = "ina226-mgtyvccaux";
|
|
reg = <0x4d>;
|
|
shunt-resistor = <5000>; /* r1679 */
|
|
/* 1.5V @ 500mA */
|
|
};
|
|
};
|
|
i2c@4 { /* LP_I2C_SM */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <4>;
|
|
/* FIXME wires ready but chip is missing */
|
|
};
|
|
i2c@5 { /* zSFP_SI570 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <5>;
|
|
si570_zsfp: clock-generator@5d { /* u192 */
|
|
#clock-cells = <0>;
|
|
compatible = "silabs,si570";
|
|
reg = <0x5d>;
|
|
temperature-stability = <50>;
|
|
factory-fout = <156250000>;
|
|
clock-frequency = <156250000>;
|
|
clock-output-names = "si570_zsfp_clk";
|
|
};
|
|
};
|
|
i2c@6 { /* USER_SI570_1 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <6>;
|
|
si570_user1: clock-generator@5d { /* u205 */
|
|
#clock-cells = <0>;
|
|
compatible = "silabs,si570";
|
|
reg = <0x5f>;
|
|
temperature-stability = <50>;
|
|
factory-fout = <100000000>;
|
|
clock-frequency = <100000000>;
|
|
clock-output-names = "si570_user1";
|
|
};
|
|
|
|
};
|
|
i2c@7 { /* USER_SI570_2 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <7>;
|
|
/* FIXME wires ready but chip is missing */
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c1 { /* i2c1 MIO 36-37 */
|
|
status = "okay";
|
|
clock-frequency = <400000>;
|
|
|
|
i2c-mux@74 { /* u35 */
|
|
compatible = "nxp,pca9548";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x74>;
|
|
i2c-mux-idle-disconnect;
|
|
/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
|
|
dc_i2c: i2c@0 { /* DC_I2C */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
/* Use for storing information about SC board */
|
|
eeprom: eeprom@54 { /* u34 - m24128 16kB */
|
|
compatible = "st,24c128", "atmel,24c128";
|
|
reg = <0x54>; /* 0x5c too */
|
|
};
|
|
si570_ref_clk: clock-generator@5d { /* u32 */
|
|
#clock-cells = <0>;
|
|
compatible = "silabs,si570";
|
|
reg = <0x5d>;
|
|
temperature-stability = <50>;
|
|
factory-fout = <33333333>;
|
|
clock-frequency = <33333333>;
|
|
clock-output-names = "ref_clk";
|
|
silabs,skip-recall;
|
|
};
|
|
/* and connector J212D */
|
|
};
|
|
fmc1: i2c@1 { /* FMCP1_IIC */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
/* FIXME connection to Samtec J51C */
|
|
/* expected eeprom 0x50 FMC cards */
|
|
};
|
|
fmc2: i2c@2 { /* FMCP2_IIC */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <2>;
|
|
/* FIXME connection to Samtec J53C */
|
|
/* expected eeprom 0x50 FMC cards */
|
|
};
|
|
i2c@3 { /* DDR4_DIMM1 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <3>;
|
|
si570_ddr_dimm1: clock-generator@60 { /* u2 */
|
|
#clock-cells = <0>;
|
|
compatible = "silabs,si570";
|
|
reg = <0x60>;
|
|
temperature-stability = <50>;
|
|
factory-fout = <200000000>;
|
|
clock-frequency = <200000000>;
|
|
clock-output-names = "si570_ddrdimm1_clk";
|
|
silabs,skip-recall;
|
|
};
|
|
};
|
|
i2c@4 { /* LPDDR4_SI570_CLK2 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <4>;
|
|
si570_lpddr4clk2: clock-generator@60 { /* u3 */
|
|
#clock-cells = <0>;
|
|
compatible = "silabs,si570";
|
|
reg = <0x60>;
|
|
temperature-stability = <50>;
|
|
factory-fout = <200000000>;
|
|
clock-frequency = <200000000>;
|
|
clock-output-names = "si570_lpddr4_clk2";
|
|
};
|
|
};
|
|
i2c@5 { /* LPDDR4_SI570_CLK1 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <5>;
|
|
si570_lpddr4clk1: clock-generator@60 { /* u4 */
|
|
#clock-cells = <0>;
|
|
compatible = "silabs,si570";
|
|
reg = <0x60>;
|
|
temperature-stability = <50>;
|
|
factory-fout = <200000000>;
|
|
clock-frequency = <200000000>;
|
|
clock-output-names = "si570_lpddr4_clk1";
|
|
};
|
|
};
|
|
i2c@6 { /* HSDP_SI570 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <6>;
|
|
si570_hsdp: clock-generator@5d { /* u5 */
|
|
#clock-cells = <0>;
|
|
compatible = "silabs,si570";
|
|
reg = <0x5d>;
|
|
temperature-stability = <50>;
|
|
factory-fout = <156250000>;
|
|
clock-frequency = <156250000>;
|
|
clock-output-names = "si570_hsdp_clk";
|
|
};
|
|
};
|
|
i2c@7 { /* 8A34001 - U219B and J310 connector */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <7>;
|
|
};
|
|
};
|
|
i2c-mux@75 { /* u214 */
|
|
compatible = "nxp,pca9548";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x75>;
|
|
i2c-mux-idle-disconnect;
|
|
i2c@0 { /* SFP0_IIC */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
/* SFP0 */
|
|
};
|
|
i2c@1 { /* SFP1_IIC */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
/* SFP1 */
|
|
};
|
|
i2c@2 { /* QSFP1_I2C */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <2>;
|
|
/* QSFP1 */
|
|
};
|
|
/* 3 - 7 unused */
|
|
};
|
|
};
|
|
|
|
&xilinx_ams {
|
|
status = "okay";
|
|
};
|
|
|
|
&ams_ps {
|
|
status = "okay";
|
|
};
|
|
|
|
&ams_pl {
|
|
status = "okay";
|
|
};
|