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On Tegra186, some I2C controllers are directly controlled by the main CPU, whereas others are controlled by the BPMP, and can only be accessed by the main CPU via IPC requests to the BPMP. This driver covers the latter case. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
176 lines
5.8 KiB
Text
176 lines
5.8 KiB
Text
#
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# I2C subsystem configuration
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#
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menu "I2C support"
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config DM_I2C
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bool "Enable Driver Model for I2C drivers"
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depends on DM
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help
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Enable driver model for I2C. The I2C uclass interface: probe, read,
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write and speed, is implemented with the bus drivers operations,
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which provide methods for bus setting and data transfer. Each chip
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device (bus child) info is kept as parent platdata. The interface
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is defined in include/i2c.h. When i2c bus driver supports the i2c
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uclass, but the device drivers not, then DM_I2C_COMPAT config can
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be used as compatibility layer.
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config DM_I2C_COMPAT
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bool "Enable I2C compatibility layer"
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depends on DM
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help
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Enable old-style I2C functions for compatibility with existing code.
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This option can be enabled as a temporary measure to avoid needing
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to convert all code for a board in a single commit. It should not
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be enabled for any board in an official release.
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config I2C_CROS_EC_TUNNEL
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tristate "Chrome OS EC tunnel I2C bus"
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depends on CROS_EC
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help
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This provides an I2C bus that will tunnel i2c commands through to
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the other side of the Chrome OS EC to the I2C bus connected there.
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This will work whatever the interface used to talk to the EC (SPI,
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I2C or LPC). Some Chromebooks use this when the hardware design
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does not allow direct access to the main PMIC from the AP.
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config I2C_CROS_EC_LDO
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bool "Provide access to LDOs on the Chrome OS EC"
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depends on CROS_EC
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---help---
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On many Chromebooks the main PMIC is inaccessible to the AP. This is
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often dealt with by using an I2C pass-through interface provided by
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the EC. On some unfortunate models (e.g. Spring) the pass-through
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is not available, and an LDO message is available instead. This
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option enables a driver which provides very basic access to those
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regulators, via the EC. We implement this as an I2C bus which
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emulates just the TPS65090 messages we know about. This is done to
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avoid duplicating the logic in the TPS65090 regulator driver for
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enabling/disabling an LDO.
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config DM_I2C_GPIO
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bool "Enable Driver Model for software emulated I2C bus driver"
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depends on DM_I2C && DM_GPIO
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help
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Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
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configuration is given by the device tree. Kernel-style device tree
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bindings are supported.
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Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
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config SYS_I2C_FSL
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bool "Freescale I2C bus driver"
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depends on DM_I2C
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help
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Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
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MPC85xx processors.
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config SYS_I2C_CADENCE
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tristate "Cadence I2C Controller"
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depends on DM_I2C && (ARCH_ZYNQ || ARM64)
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help
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Say yes here to select Cadence I2C Host Controller. This controller is
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e.g. used by Xilinx Zynq.
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config SYS_I2C_DW
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bool "Designware I2C Controller"
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default n
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help
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Say yes here to select the Designware I2C Host Controller. This
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controller is used in various SoCs, e.g. the ST SPEAr, Altera
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SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
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config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
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bool "DW I2C Enable Status Register not supported"
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depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
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TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
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default y
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help
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Some versions of the Designware I2C controller do not support the
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enable status register. This config option can be enabled in such
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cases.
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config SYS_I2C_INTEL
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bool "Intel I2C/SMBUS driver"
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depends on DM_I2C
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help
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Add support for the Intel SMBUS driver. So far this driver is just
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a stub which perhaps some basic init. There is no implementation of
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the I2C API meaning that any I2C operations will immediately fail
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for now.
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config SYS_I2C_ROCKCHIP
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bool "Rockchip I2C driver"
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depends on DM_I2C
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help
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Add support for the Rockchip I2C driver. This is used with various
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Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
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have several I2C ports and all are provided, controled by the
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device tree.
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config SYS_I2C_SANDBOX
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bool "Sandbox I2C driver"
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depends on SANDBOX && DM_I2C
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help
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Enable I2C support for sandbox. This is an emulation of a real I2C
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bus. Devices can be attached to the bus using the device tree
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which specifies the driver to use. As an example, see this device
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tree fragment from sandbox.dts. It shows that the I2C bus has a
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single EEPROM at address 0x2c (7-bit address) which is emulated by
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the driver for "sandbox,i2c-eeprom", which is in
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drivers/misc/i2c_eeprom_emul.c.
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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compatible = "sandbox,i2c";
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clock-frequency = <400000>;
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eeprom@2c {
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reg = <0x2c>;
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compatible = "i2c-eeprom";
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emul {
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compatible = "sandbox,i2c-eeprom";
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sandbox,filename = "i2c.bin";
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sandbox,size = <128>;
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};
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};
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};
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config SYS_I2C_UNIPHIER
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bool "UniPhier I2C driver"
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depends on ARCH_UNIPHIER && DM_I2C
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default y
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help
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Support for UniPhier I2C controller driver. This I2C controller
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is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
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config SYS_I2C_UNIPHIER_F
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bool "UniPhier FIFO-builtin I2C driver"
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depends on ARCH_UNIPHIER && DM_I2C
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default y
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help
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Support for UniPhier FIFO-builtin I2C controller driver.
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This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
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config SYS_I2C_MVTWSI
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bool "Marvell I2C driver"
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depends on DM_I2C
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help
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Support for Marvell I2C controllers as used on the orion5x and
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kirkwood SoC families.
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config TEGRA186_BPMP_I2C
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bool "Enable Tegra186 BPMP-based I2C driver"
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depends on TEGRA186_BPMP
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help
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Support for Tegra I2C controllers managed by the BPMP (Boot and
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Power Management Processor). On Tegra186, some I2C controllers are
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directly controlled by the main CPU, whereas others are controlled
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by the BPMP, and can only be accessed by the main CPU via IPC
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requests to the BPMP. This driver covers the latter case.
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source "drivers/i2c/muxes/Kconfig"
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endmenu
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