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https://github.com/AsahiLinux/u-boot
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9c22aec410
Masking clock gate, reset register bits based on the probed controller is proper only due to the assumption that masking should start with 0 even thought the controller has separate PHY or shared between OTG. unfortunately these are fixed due to lack of separate clock, reset drivers. Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) so we need to start reg_mask 0 - 2. This patch calculated the mask, based on the register base so that we can get the proper bits to set with respect to probed controller. We even do this masking by using PHY index specifier from dt, but dev_read_addr_size is failing for 64-bit boards. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
220 lines
6.2 KiB
C
220 lines
6.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*/
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#ifndef _SUNXI_CPU_SUN4I_H
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#define _SUNXI_CPU_SUN4I_H
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#define SUNXI_SRAM_A1_BASE 0x00000000
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#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */
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#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
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#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
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#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
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#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
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#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
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#define SUNXI_DE2_BASE 0x01000000
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#ifdef CONFIG_MACH_SUN8I_A83T
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#define SUNXI_CPUCFG_BASE 0x01700000
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#endif
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#define SUNXI_SRAMC_BASE 0x01c00000
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#define SUNXI_DRAMC_BASE 0x01c01000
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#define SUNXI_DMA_BASE 0x01c02000
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#define SUNXI_NFC_BASE 0x01c03000
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#define SUNXI_TS_BASE 0x01c04000
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#define SUNXI_SPI0_BASE 0x01c05000
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#define SUNXI_SPI1_BASE 0x01c06000
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#define SUNXI_MS_BASE 0x01c07000
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#define SUNXI_TVD_BASE 0x01c08000
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#define SUNXI_CSI0_BASE 0x01c09000
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#ifndef CONFIG_MACH_SUNXI_H3_H5
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#define SUNXI_TVE0_BASE 0x01c0a000
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#endif
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#define SUNXI_EMAC_BASE 0x01c0b000
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#define SUNXI_LCD0_BASE 0x01c0C000
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#define SUNXI_LCD1_BASE 0x01c0d000
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#define SUNXI_VE_BASE 0x01c0e000
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#define SUNXI_MMC0_BASE 0x01c0f000
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#define SUNXI_MMC1_BASE 0x01c10000
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#define SUNXI_MMC2_BASE 0x01c11000
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#define SUNXI_MMC3_BASE 0x01c12000
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#ifdef CONFIG_SUNXI_GEN_SUN4I
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#define SUNXI_USB0_BASE 0x01c13000
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#define SUNXI_USB1_BASE 0x01c14000
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#endif
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#define SUNXI_SS_BASE 0x01c15000
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#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
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#define SUNXI_HDMI_BASE 0x01c16000
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#endif
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#define SUNXI_SPI2_BASE 0x01c17000
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#define SUNXI_SATA_BASE 0x01c18000
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#ifdef CONFIG_SUNXI_GEN_SUN4I
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#define SUNXI_PATA_BASE 0x01c19000
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#define SUNXI_ACE_BASE 0x01c1a000
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#define SUNXI_TVE1_BASE 0x01c1b000
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#define SUNXI_USB2_BASE 0x01c1c000
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#endif
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
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#define SUNXI_USBPHY_BASE 0x01c19000
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#define SUNXI_USB0_BASE SUNXI_USBPHY_BASE
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#define SUNXI_USB1_BASE 0x01c1a000
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#define SUNXI_USB2_BASE 0x01c1b000
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#define SUNXI_USB3_BASE 0x01c1c000
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#define SUNXI_USB4_BASE 0x01c1d000
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#else
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#define SUNXI_USB0_BASE 0x01c19000
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#define SUNXI_USB1_BASE 0x01c1a000
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#define SUNXI_USB2_BASE 0x01c1b000
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#endif
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#endif
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#define SUNXI_CSI1_BASE 0x01c1d000
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#define SUNXI_TZASC_BASE 0x01c1e000
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#define SUNXI_SPI3_BASE 0x01c1f000
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#define SUNXI_CCM_BASE 0x01c20000
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#define SUNXI_INTC_BASE 0x01c20400
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#define SUNXI_PIO_BASE 0x01c20800
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#define SUNXI_TIMER_BASE 0x01c20c00
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#ifndef CONFIG_SUNXI_GEN_SUN6I
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#define SUNXI_PWM_BASE 0x01c20e00
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#endif
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#define SUNXI_SPDIF_BASE 0x01c21000
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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#define SUNXI_PWM_BASE 0x01c21400
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#else
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#define SUNXI_AC97_BASE 0x01c21400
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#endif
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#define SUNXI_IR0_BASE 0x01c21800
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#define SUNXI_IR1_BASE 0x01c21c00
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#define SUNXI_IIS_BASE 0x01c22400
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#define SUNXI_LRADC_BASE 0x01c22800
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#define SUNXI_AD_DA_BASE 0x01c22c00
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#define SUNXI_KEYPAD_BASE 0x01c23000
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#define SUNXI_TZPC_BASE 0x01c23400
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#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUNXI_H3_H5) || \
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defined(CONFIG_MACH_SUN50I)
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/* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */
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#define SUNXI_SIDC_BASE 0x01c14000
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#define SUNXI_SID_BASE 0x01c14200
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#else
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#define SUNXI_SID_BASE 0x01c23800
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#endif
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#define SUNXI_SJTAG_BASE 0x01c23c00
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#define SUNXI_TP_BASE 0x01c25000
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#define SUNXI_PMU_BASE 0x01c25400
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#if defined CONFIG_MACH_SUN7I || defined CONFIG_MACH_SUN8I_R40
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#define SUNXI_CPUCFG_BASE 0x01c25c00
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#endif
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#define SUNXI_UART0_BASE 0x01c28000
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#define SUNXI_UART1_BASE 0x01c28400
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#define SUNXI_UART2_BASE 0x01c28800
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#define SUNXI_UART3_BASE 0x01c28c00
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#define SUNXI_UART4_BASE 0x01c29000
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#define SUNXI_UART5_BASE 0x01c29400
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#define SUNXI_UART6_BASE 0x01c29800
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#define SUNXI_UART7_BASE 0x01c29c00
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#define SUNXI_PS2_0_BASE 0x01c2a000
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#define SUNXI_PS2_1_BASE 0x01c2a400
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#define SUNXI_TWI0_BASE 0x01c2ac00
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#define SUNXI_TWI1_BASE 0x01c2b000
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#define SUNXI_TWI2_BASE 0x01c2b400
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#ifdef CONFIG_MACH_SUN6I
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#define SUNXI_TWI3_BASE 0x01c0b800
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#endif
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#ifdef CONFIG_MACH_SUN7I
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#define SUNXI_TWI3_BASE 0x01c2b800
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#define SUNXI_TWI4_BASE 0x01c2c000
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#endif
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#define SUNXI_CAN_BASE 0x01c2bc00
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#define SUNXI_SCR_BASE 0x01c2c400
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#ifndef CONFIG_MACH_SUN6I
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#define SUNXI_GPS_BASE 0x01c30000
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#define SUNXI_MALI400_BASE 0x01c40000
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#define SUNXI_GMAC_BASE 0x01c50000
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#else
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#define SUNXI_GMAC_BASE 0x01c30000
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#endif
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#define SUNXI_DRAM_COM_BASE 0x01c62000
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#define SUNXI_DRAM_CTL0_BASE 0x01c63000
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#define SUNXI_DRAM_CTL1_BASE 0x01c64000
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#define SUNXI_DRAM_PHY0_BASE 0x01c65000
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#define SUNXI_DRAM_PHY1_BASE 0x01c66000
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#define SUNXI_GIC400_BASE 0x01c80000
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/* module sram */
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#define SUNXI_SRAM_C_BASE 0x01d00000
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#ifndef CONFIG_MACH_SUN8I_H3
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#define SUNXI_DE_FE0_BASE 0x01e00000
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#else
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#define SUNXI_TVE0_BASE 0x01e00000
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#endif
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#define SUNXI_DE_FE1_BASE 0x01e20000
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#define SUNXI_DE_BE0_BASE 0x01e60000
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#ifndef CONFIG_MACH_SUN50I_H5
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#define SUNXI_DE_BE1_BASE 0x01e40000
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#else
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#define SUNXI_TVE0_BASE 0x01e40000
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#endif
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#define SUNXI_MP_BASE 0x01e80000
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#define SUNXI_AVG_BASE 0x01ea0000
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#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
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#define SUNXI_HDMI_BASE 0x01ee0000
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#endif
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#define SUNXI_RTC_BASE 0x01f00000
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#define SUNXI_PRCM_BASE 0x01f01400
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#if defined CONFIG_SUNXI_GEN_SUN6I && \
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!defined CONFIG_MACH_SUN8I_A83T && \
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!defined CONFIG_MACH_SUN8I_R40
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#define SUNXI_CPUCFG_BASE 0x01f01c00
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#endif
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#define SUNXI_R_TWI_BASE 0x01f02400
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#define SUNXI_R_UART_BASE 0x01f02800
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#define SUNXI_R_PIO_BASE 0x01f02c00
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#define SUN6I_P2WI_BASE 0x01f03400
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#define SUNXI_RSB_BASE 0x01f03400
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/* CoreSight Debug Module */
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#define SUNXI_CSDM_BASE 0x3f500000
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#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */
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#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */
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#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c)
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/* SS bonding ids used for cpu identification */
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#define SUNXI_SS_BOND_ID_A31 4
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#define SUNXI_SS_BOND_ID_A31S 5
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#ifndef __ASSEMBLY__
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void sunxi_board_init(void);
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void sunxi_reset(void);
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int sunxi_get_ss_bonding_id(void);
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int sunxi_get_sid(unsigned int *sid);
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#endif /* __ASSEMBLY__ */
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#endif /* _SUNXI_CPU_SUN4I_H */
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