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https://github.com/AsahiLinux/u-boot
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2395625209
The GW74xx is based on the i.MX 8M Plus SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- Gateworks System Controller
- PCIe Gen 3.0 switch (build option)
- USB 3.0 HUB
- USB Type-C front panel connector
- GPS
- 3-axis accelerometer
- CAN bus
- 6x GbE RJ45 front-panel jacks
- 1x IMX8M FEC RGMII GbE (with Passive PoE)
- 5x IMX8M EQOS RGMII 6 port GbE Switch
(1x with 802.3af class 5 Active PoE)
- RS232/RS485/RS422 serial transceiver
- MIPI header (DSI/CSI/GPIO/PWM/I2S)
- DigI/O header (UART/GPIO/I2C/ADC)
- 802.11ac WiFi
- Bluetooth BLE
- 3x MiniPCIe sockets with PCI/USB
- 1x M.2 Socket with USB2.0, PCIe, and dual-SIM
- PMIC
- Wide range DC input supply (8V to 60V DC)
Do the following to add support for this and future imx8mp-venice boards:
- add dts
- add DRAM config
- add PMIC config
- add IMX8MP support in spl.c and venice.c
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
159 lines
3.6 KiB
Text
159 lines
3.6 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 Gateworks Corporation
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*/
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/dts-v1/;
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#include "imx8mp.dtsi"
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/ {
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model = "Gateworks Venice i.MX8MP board";
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compatible = "gateworks,imx8mp-venice", "fsl,imx8mp";
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chosen {
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stdout-path = &uart2;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0 0x80000000>;
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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gsc: gsc@20 {
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compatible = "gw,gsc";
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reg = <0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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eeprom@51 {
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compatible = "atmel,24c02";
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reg = <0x51>;
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pagesize = <16>;
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};
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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eeprom@52 {
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compatible = "atmel,24c32";
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reg = <0x52>;
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pagesize = <32>;
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};
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};
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/* console */
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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/* eMMC */
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&usdhc3 {
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assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
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assigned-clock-rates = <400000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
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MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
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MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
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MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
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MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
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MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
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MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
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MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
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MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
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MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
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MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
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MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
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MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
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MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
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>;
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};
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pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
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fsl,pins = <
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MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
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MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
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MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
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MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
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MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
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MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
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MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
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MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
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MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
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MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
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MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
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>;
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};
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pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
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fsl,pins = <
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MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
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MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
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MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
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MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
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MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
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MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
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MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
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MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
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MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
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MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
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MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
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>;
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};
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pinctrl_wdog: wdoggrp {
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fsl,pins = <
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MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
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>;
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};
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};
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