mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-14 23:33:00 +00:00
a09fea1d28
- In ARMv8 NXP Layerscape platforms we also need to make use of CONFIG_SYS_RELOC_GD_ENV_ADDR now, do so. - On ENV_IS_IN_REMOTE, CONFIG_ENV_OFFSET is never used, drop the define to 0. - Add Kconfig entry for ENV_ADDR. - Make ENV_ADDR / ENV_OFFSET depend on the env locations that use it. - Add ENV_xxx_REDUND options that depend on their primary option and SYS_REDUNDAND_ENVIRONMENT - On a number of PowerPC platforms, use SPL_ENV_ADDR not CONFIG_ENV_ADDR for the pre-main-U-Boot environment location. - On ENV_IS_IN_SPI_FLASH, check not for CONFIG_ENV_ADDR being set but rather it being non-zero, as it will now be zero by default. - Rework the env_offset absolute in env/embedded.o to not use CONFIG_ENV_OFFSET as it was the only use of ENV_OFFSET within ENV_IS_IN_FLASH. - Migrate all platforms. Cc: Wolfgang Denk <wd@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
157 lines
4 KiB
Text
157 lines
4 KiB
Text
CONFIG_PPC=y
|
|
CONFIG_SYS_TEXT_BASE=0xFE000000
|
|
CONFIG_ENV_SIZE=0x2000
|
|
CONFIG_ENV_SECT_SIZE=0x20000
|
|
CONFIG_SYS_CLK_FREQ=66000000
|
|
CONFIG_MPC83xx=y
|
|
CONFIG_HIGH_BATS=y
|
|
CONFIG_TARGET_MPC832XEMDS=y
|
|
CONFIG_CORE_PLL_RATIO_2_1=y
|
|
CONFIG_QUICC_MULT_FACTOR_3=y
|
|
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
|
|
CONFIG_BAT0=y
|
|
CONFIG_BAT0_NAME="SDRAM"
|
|
CONFIG_BAT0_BASE=0x00000000
|
|
CONFIG_BAT0_LENGTH_256_MBYTES=y
|
|
CONFIG_BAT0_ACCESS_RW=y
|
|
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
|
|
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
|
|
CONFIG_BAT0_USER_MODE_VALID=y
|
|
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
|
|
CONFIG_BAT1=y
|
|
CONFIG_BAT1_NAME="IMMR"
|
|
CONFIG_BAT1_BASE=0xE0000000
|
|
CONFIG_BAT1_LENGTH_4_MBYTES=y
|
|
CONFIG_BAT1_ACCESS_RW=y
|
|
CONFIG_BAT1_ICACHE_INHIBITED=y
|
|
CONFIG_BAT1_ICACHE_GUARDED=y
|
|
CONFIG_BAT1_DCACHE_INHIBITED=y
|
|
CONFIG_BAT1_DCACHE_GUARDED=y
|
|
CONFIG_BAT1_USER_MODE_VALID=y
|
|
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
|
|
CONFIG_BAT2=y
|
|
CONFIG_BAT2_NAME="BCSR"
|
|
CONFIG_BAT2_BASE=0xF8000000
|
|
CONFIG_BAT2_ACCESS_RW=y
|
|
CONFIG_BAT2_ICACHE_INHIBITED=y
|
|
CONFIG_BAT2_ICACHE_GUARDED=y
|
|
CONFIG_BAT2_DCACHE_INHIBITED=y
|
|
CONFIG_BAT2_DCACHE_GUARDED=y
|
|
CONFIG_BAT2_USER_MODE_VALID=y
|
|
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
|
|
CONFIG_BAT3=y
|
|
CONFIG_BAT3_NAME="FLASH"
|
|
CONFIG_BAT3_BASE=0xFE000000
|
|
CONFIG_BAT3_LENGTH_32_MBYTES=y
|
|
CONFIG_BAT3_ACCESS_RW=y
|
|
CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y
|
|
CONFIG_BAT3_DCACHE_INHIBITED=y
|
|
CONFIG_BAT3_DCACHE_GUARDED=y
|
|
CONFIG_BAT3_USER_MODE_VALID=y
|
|
CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
|
|
CONFIG_BAT5=y
|
|
CONFIG_BAT5_NAME="STACK_IN_DCACHE"
|
|
CONFIG_BAT5_BASE=0xE6000000
|
|
CONFIG_BAT5_ACCESS_RW=y
|
|
CONFIG_BAT5_USER_MODE_VALID=y
|
|
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
|
|
CONFIG_BAT6=y
|
|
CONFIG_BAT6_NAME="PCI_MEM_PHYS"
|
|
CONFIG_BAT6_BASE=0x80000000
|
|
CONFIG_BAT6_LENGTH_256_MBYTES=y
|
|
CONFIG_BAT6_ACCESS_RW=y
|
|
CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
|
|
CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
|
|
CONFIG_BAT6_USER_MODE_VALID=y
|
|
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
|
|
CONFIG_BAT7=y
|
|
CONFIG_BAT7_NAME="PCI1_MMIO_PHYS"
|
|
CONFIG_BAT7_BASE=0x90000000
|
|
CONFIG_BAT7_LENGTH_256_MBYTES=y
|
|
CONFIG_BAT7_ACCESS_RW=y
|
|
CONFIG_BAT7_ICACHE_INHIBITED=y
|
|
CONFIG_BAT7_ICACHE_GUARDED=y
|
|
CONFIG_BAT7_DCACHE_INHIBITED=y
|
|
CONFIG_BAT7_DCACHE_GUARDED=y
|
|
CONFIG_BAT7_USER_MODE_VALID=y
|
|
CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
|
|
CONFIG_LBLAW0=y
|
|
CONFIG_LBLAW0_BASE=0xFE000000
|
|
CONFIG_LBLAW0_NAME="FLASH"
|
|
CONFIG_LBLAW0_LENGTH_32_MBYTES=y
|
|
CONFIG_LBLAW1=y
|
|
CONFIG_LBLAW1_BASE=0xF8000000
|
|
CONFIG_LBLAW1_NAME="BCSR"
|
|
CONFIG_LBLAW1_LENGTH_32_KBYTES=y
|
|
CONFIG_LBLAW3=y
|
|
CONFIG_LBLAW3_BASE=0xF8008000
|
|
CONFIG_LBLAW3_NAME="PIB"
|
|
CONFIG_LBLAW3_LENGTH_64_KBYTES=y
|
|
CONFIG_ELBC_BR0_OR0=y
|
|
CONFIG_BR0_OR0_NAME="FLASH"
|
|
CONFIG_BR0_OR0_BASE=0xFE000000
|
|
CONFIG_BR0_PORTSIZE_16BIT=y
|
|
CONFIG_OR0_AM_16_MBYTES=y
|
|
CONFIG_OR0_XAM_SET=y
|
|
CONFIG_OR0_SCY_15=y
|
|
CONFIG_OR0_CSNT_EARLIER=y
|
|
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
|
|
CONFIG_OR0_XACS_EXTENDED=y
|
|
CONFIG_OR0_TRLX_RELAXED=y
|
|
CONFIG_OR0_EHTR_8_CYCLE=y
|
|
CONFIG_OR0_EAD_EXTRA=y
|
|
CONFIG_ELBC_BR1_OR1=y
|
|
CONFIG_BR1_OR1_NAME="BCSR"
|
|
CONFIG_BR1_OR1_BASE=0xF8000000
|
|
CONFIG_OR1_XAM_SET=y
|
|
CONFIG_OR1_SCY_15=y
|
|
CONFIG_OR1_CSNT_EARLIER=y
|
|
CONFIG_OR1_XACS_EXTENDED=y
|
|
CONFIG_OR1_TRLX_RELAXED=y
|
|
CONFIG_OR1_EHTR_8_CYCLE=y
|
|
CONFIG_OR1_EAD_EXTRA=y
|
|
CONFIG_ELBC_BR2_OR2=y
|
|
CONFIG_BR2_OR2_NAME="PIB1"
|
|
CONFIG_BR2_OR2_BASE=0xF8008000
|
|
CONFIG_OR2_XAM_SET=y
|
|
CONFIG_OR2_SCY_15=y
|
|
CONFIG_OR2_CSNT_EARLIER=y
|
|
CONFIG_OR2_XACS_EXTENDED=y
|
|
CONFIG_OR2_TRLX_RELAXED=y
|
|
CONFIG_OR2_EHTR_8_CYCLE=y
|
|
CONFIG_OR2_EAD_EXTRA=y
|
|
CONFIG_ELBC_BR3_OR3=y
|
|
CONFIG_BR3_OR3_NAME="PIB2"
|
|
CONFIG_BR3_OR3_BASE=0xF8010000
|
|
CONFIG_OR3_XAM_SET=y
|
|
CONFIG_OR3_SCY_15=y
|
|
CONFIG_OR3_CSNT_EARLIER=y
|
|
CONFIG_OR3_XACS_EXTENDED=y
|
|
CONFIG_OR3_TRLX_RELAXED=y
|
|
CONFIG_OR3_EHTR_8_CYCLE=y
|
|
CONFIG_OR3_EAD_EXTRA=y
|
|
CONFIG_HID0_FINAL_EMCP=y
|
|
CONFIG_HID0_FINAL_ICE=y
|
|
CONFIG_HID2_HBE=y
|
|
CONFIG_LCRR_CLKDIV_2=y
|
|
CONFIG_OF_BOARD_SETUP=y
|
|
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
|
|
CONFIG_BOOTDELAY=6
|
|
CONFIG_BOARD_EARLY_INIT_R=y
|
|
CONFIG_HUSH_PARSER=y
|
|
CONFIG_CMD_IMLS=y
|
|
CONFIG_CMD_ASKENV=y
|
|
CONFIG_CMD_I2C=y
|
|
CONFIG_CMD_PCI=y
|
|
# CONFIG_CMD_SETEXPR is not set
|
|
CONFIG_CMD_PING=y
|
|
CONFIG_ENV_ADDR=0xFE080000
|
|
# CONFIG_MMC is not set
|
|
CONFIG_MTD_NOR_FLASH=y
|
|
CONFIG_FLASH_CFI_DRIVER=y
|
|
CONFIG_SYS_FLASH_PROTECTION=y
|
|
CONFIG_SYS_FLASH_CFI=y
|
|
CONFIG_QE=y
|
|
CONFIG_SYS_NS16550=y
|
|
CONFIG_OF_LIBFDT=y
|