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https://github.com/AsahiLinux/u-boot
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7e2ec1de1d
The SerDes initialization should be finished before negating the reset signal according to the reference manual. This isn't an issue on real hardware, but we'd better stick to the specifications anyway. Suggested-by: Liu Dave <DaveLiu@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
155 lines
4 KiB
C
155 lines
4 KiB
C
/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <common.h>
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#include <mpc83xx.h>
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#include <pci.h>
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#include <i2c.h>
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#include <fdt_support.h>
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#include <asm/fsl_i2c.h>
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#include <asm/fsl_serdes.h>
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#if defined(CONFIG_PCI)
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static struct pci_region pci_regions[] = {
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{
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bus_start: CONFIG_SYS_PCI_MEM_BASE,
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phys_start: CONFIG_SYS_PCI_MEM_PHYS,
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size: CONFIG_SYS_PCI_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CONFIG_SYS_PCI_MMIO_BASE,
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phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
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size: CONFIG_SYS_PCI_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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{
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bus_start: CONFIG_SYS_PCI_IO_BASE,
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phys_start: CONFIG_SYS_PCI_IO_PHYS,
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size: CONFIG_SYS_PCI_IO_SIZE,
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flags: PCI_REGION_IO
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}
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};
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static struct pci_region pcie_regions_0[] = {
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{
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.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
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.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
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.size = CONFIG_SYS_PCIE1_MEM_SIZE,
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.flags = PCI_REGION_MEM,
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},
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{
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.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
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.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
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.size = CONFIG_SYS_PCIE1_IO_SIZE,
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.flags = PCI_REGION_IO,
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},
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};
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static struct pci_region pcie_regions_1[] = {
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{
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.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
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.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
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.size = CONFIG_SYS_PCIE2_MEM_SIZE,
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.flags = PCI_REGION_MEM,
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},
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{
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.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
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.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
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.size = CONFIG_SYS_PCIE2_IO_SIZE,
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.flags = PCI_REGION_IO,
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},
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};
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static int is_pex_x2(void)
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{
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const char *pex_x2 = getenv("pex_x2");
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if (pex_x2 && !strcmp(pex_x2, "yes"))
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return 1;
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return 0;
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}
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void pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile sysconf83xx_t *sysconf = &immr->sysconf;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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volatile law83xx_t *pcie_law = sysconf->pcielaw;
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struct pci_region *reg[] = { pci_regions };
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struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
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u32 spridr = in_be32(&immr->sysconf.spridr);
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int pex2 = is_pex_x2();
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if (board_pci_host_broken())
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goto skip_pci;
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/* Enable all 5 PCI_CLK_OUTPUTS */
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clk->occr |= 0xf8000000;
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udelay(2000);
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/* Configure PCI Local Access Windows */
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pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
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pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
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udelay(2000);
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mpc83xx_pci_init(1, reg, 0);
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skip_pci:
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/* There is no PEX in MPC8379 parts. */
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if (PARTID_NO_E(spridr) == SPR_8379)
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return;
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if (pex2)
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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else
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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/* Configure the clock for PCIE controller */
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clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
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SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
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/* Deassert the resets in the control register */
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out_be32(&sysconf->pecr1, 0xE0008000);
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if (!pex2)
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out_be32(&sysconf->pecr2, 0xE0008000);
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udelay(2000);
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/* Configure PCI Express Local Access Windows */
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out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
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out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
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out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
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out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
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mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg, 0);
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}
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void ft_pcie_fixup(void *blob, bd_t *bd)
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{
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const char *status = "disabled (PCIE1 is x2)";
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if (!is_pex_x2())
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return;
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do_fixup_by_path(blob, "pci2", "status", status,
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strlen(status) + 1, 1);
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}
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#endif /* CONFIG_PCI */
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