mirror of
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ff9112df8b
With the upcoming addition of the Armada 38x DDR support, which is not
compatible to the Armada XP DDR init code, we need to introduce a new
directory infrastructure. To support multiple Marvell DDR controller.
This will be the new structure:
drivers/ddr/marvell/axp
Supporting Armada XP (AXP) devices (and perhaps Armada 370)
drivers/ddr/marvell/a38x
Supporting Armada 38x devices (and perhaps Armada 39x)
Signed-off-by: Stefan Roese <sr@denx.de>
392 lines
14 KiB
C
392 lines
14 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __DDR3_TRAINING_H
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#define __DDR3_TRAINING_H
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#include "ddr3_init.h"
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#ifdef MV88F78X60
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#include "ddr3_axp.h"
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#elif defined(MV88F67XX)
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#include "ddr3_a370.h"
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#elif defined(MV88F672X)
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#include "ddr3_a375.h"
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#endif
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/* The following is a list of Marvell status */
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#define MV_ERROR (-1)
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#define MV_OK (0x00) /* Operation succeeded */
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#define MV_FAIL (0x01) /* Operation failed */
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#define MV_BAD_VALUE (0x02) /* Illegal value (general) */
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#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */
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#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */
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#define MV_BAD_PTR (0x05) /* Illegal pointer value */
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#define MV_BAD_SIZE (0x06) /* Illegal size */
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#define MV_BAD_STATE (0x07) /* Illegal state of state machine */
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#define MV_SET_ERROR (0x08) /* Set operation failed */
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#define MV_GET_ERROR (0x09) /* Get operation failed */
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#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */
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#define MV_NOT_FOUND (0x0B) /* Item not found */
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#define MV_NO_MORE (0x0C) /* No more items found */
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#define MV_NO_SUCH (0x0D) /* No such item */
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#define MV_TIMEOUT (0x0E) /* Time Out */
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#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */
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#define MV_NOT_SUPPORTED (0x10) /* This request is not support */
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#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/
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#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */
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#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
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#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
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#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
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#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */
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#define MV_HW_ERROR (0x17) /* Hardware error */
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#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
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#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
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#define MV_NOT_READY (0x1A) /* The other side is not ready yet */
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#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */
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#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */
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#define MV_NOT_STARTED (0x1D) /* Not started yet */
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#define MV_BUSY (0x1E) /* Item is busy. */
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#define MV_TERMINATE (0x1F) /* Item terminates it's work. */
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#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */
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#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */
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#define MV_WRITE_PROTECT (0x22) /* Write protected */
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#define MV_INVALID (int)(-1)
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/*
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* Debug (Enable/Disable modules) and Error report
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*/
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#ifdef BASIC_DEBUG
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#define MV_DEBUG_WL
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#define MV_DEBUG_RL
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#define MV_DEBUG_DQS_RESULTS
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#endif
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#ifdef FULL_DEBUG
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#define MV_DEBUG_WL
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#define MV_DEBUG_RL
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#define MV_DEBUG_DQS
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#define MV_DEBUG_PBS
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#define MV_DEBUG_DFS
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#define MV_DEBUG_MAIN_FULL
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#define MV_DEBUG_DFS_FULL
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#define MV_DEBUG_DQS_FULL
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#define MV_DEBUG_RL_FULL
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#define MV_DEBUG_WL_FULL
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#endif
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/*
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* General Consts
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*/
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#define SDRAM_READ_WRITE_LEN_IN_WORDS 16
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#define SDRAM_READ_WRITE_LEN_IN_DOUBLE_WORDS 8
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#define CACHE_LINE_SIZE 0x20
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#define SDRAM_CS_BASE 0x0
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#define SRAM_BASE 0x40000000
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#define SRAM_SIZE 0xFFF
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#define LEN_64BIT_STD_PATTERN 16
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#define LEN_64BIT_KILLER_PATTERN 128
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#define LEN_64BIT_SPECIAL_PATTERN 128
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#define LEN_64BIT_PBS_PATTERN 16
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#define LEN_WL_SUP_PATTERN 32
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#define LEN_16BIT_STD_PATTERN 4
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#define LEN_16BIT_KILLER_PATTERN 128
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#define LEN_16BIT_SPECIAL_PATTERN 128
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#define LEN_16BIT_PBS_PATTERN 4
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#define CMP_BYTE_SHIFT 8
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#define CMP_BYTE_MASK 0xFF
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#define PUP_SIZE 8
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#define S 0
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#define C 1
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#define P 2
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#define D 3
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#define DQS 6
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#define PS 2
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#define DS 3
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#define PE 4
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#define DE 5
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#define CS0 0
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#define MAX_DIMM_NUM 2
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#define MAX_DELAY 0x1F
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/*
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* Invertion limit and phase1 limit are WA for the RL @ 1:1 design bug -
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* Armada 370 & AXP Z1
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*/
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#define MAX_DELAY_INV_LIMIT 0x5
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#define MIN_DELAY_PHASE_1_LIMIT 0x10
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#define MAX_DELAY_INV (0x3F - MAX_DELAY_INV_LIMIT)
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#define MIN_DELAY 0
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#define MAX_PUP_NUM 9
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#define ECC_PUP 8
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#define DQ_NUM 8
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#define DQS_DQ_NUM 8
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#define INIT_WL_DELAY 13
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#define INIT_RL_DELAY 15
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#define TWLMRD_DELAY 20
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#define TCLK_3_DELAY 3
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#define ECC_BIT 8
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#define DMA_SIZE 64
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#define MV_DMA_0 0
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#define MAX_TRAINING_RETRY 10
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#define PUP_RL_MODE 0x2
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#define PUP_WL_MODE 0
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#define PUP_PBS_TX 0x10
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#define PUP_PBS_TX_DM 0x1A
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#define PUP_PBS_RX 0x30
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#define PUP_DQS_WR 0x1
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#define PUP_DQS_RD 0x3
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#define PUP_BC 10
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#define PUP_DELAY_MASK 0x1F
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#define PUP_PHASE_MASK 0x7
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#define PUP_NUM_64BIT 8
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#define PUP_NUM_32BIT 4
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#define PUP_NUM_16BIT 2
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/* control PHY registers */
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#define CNTRL_PUP_DESKEW 0x10
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/* WL */
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#define COUNT_WL_HI_FREQ 2
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#define COUNT_WL 2
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#define COUNT_WL_RFRS 9
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#define WL_HI_FREQ_SHIFT 2
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#define WL_HI_FREQ_STATE 1
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#define COUNT_HW_WL 2
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/* RL */
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/*
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* RL_MODE - this define uses the RL mode SW RL instead of the functional
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* window SW RL
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*/
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#define RL_MODE
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#define RL_WINDOW_WA
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#define MAX_PHASE_1TO1 2
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#define MAX_PHASE_2TO1 4
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#define MAX_PHASE_RL_UL_1TO1 0
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#define MAX_PHASE_RL_L_1TO1 4
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#define MAX_PHASE_RL_UL_2TO1 3
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#define MAX_PHASE_RL_L_2TO1 7
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#define RL_UNLOCK_STATE 0
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#define RL_WINDOW_STATE 1
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#define RL_FINAL_STATE 2
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#define RL_RETRY_COUNT 2
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#define COUNT_HW_RL 2
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/* PBS */
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#define MAX_PBS 31
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#define MIN_PBS 0
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#define COUNT_PBS_PATTERN 2
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#define COUNT_PBS_STARTOVER 2
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#define COUNT_PBS_REPEAT 3
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#define COUNT_PBS_COMP_RETRY_NUM 2
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#define PBS_DIFF_LIMIT 31
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#define PATTERN_PBS_TX_A 0x55555555
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#define PATTERN_PBS_TX_B 0xAAAAAAAA
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/* DQS */
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#define ADLL_ERROR 0x55
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#define ADLL_MAX 31
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#define ADLL_MIN 0
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#define MIN_WIN_SIZE 4
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#define VALID_WIN_THRS MIN_WIN_SIZE
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#define MODE_2TO1 1
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#define MODE_1TO1 0
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/*
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* Macros
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*/
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#define IS_PUP_ACTIVE(_data_, _pup_) (((_data_) >> (_pup_)) & 0x1)
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/*
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* Internal ERROR codes
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*/
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#define MV_DDR3_TRAINING_ERR_WR_LVL_HW 0xDD302001
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#define MV_DDR3_TRAINING_ERR_LOAD_PATTERNS 0xDD302002
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#define MV_DDR3_TRAINING_ERR_WR_LVL_HI_FREQ 0xDD302003
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#define MV_DDR3_TRAINING_ERR_DFS_H2L 0xDD302004
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#define MV_DDR3_TRAINING_ERR_DRAM_COMPARE 0xDD302005
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#define MV_DDR3_TRAINING_ERR_WIN_LIMITS 0xDD302006
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#define MV_DDR3_TRAINING_ERR_PUP_RANGE 0xDD302025
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#define MV_DDR3_TRAINING_ERR_DQS_LOW_LIMIT_SEARCH 0xDD302007
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#define MV_DDR3_TRAINING_ERR_DQS_HIGH_LIMIT_SEARCH 0xDD302008
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#define MV_DDR3_TRAINING_ERR_DQS_PATTERN 0xDD302009
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#define MV_DDR3_TRAINING_ERR_PBS_ADLL_SHR_1PHASE 0xDD302010
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#define MV_DDR3_TRAINING_ERR_PBS_TX_MAX_VAL 0xDD302011
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#define MV_DDR3_TRAINING_ERR_PBS_RX_PER_BIT 0xDD302012
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#define MV_DDR3_TRAINING_ERR_PBS_TX_PER_BIT 0xDD302013
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#define MV_DDR3_TRAINING_ERR_PBS_RX_MAX_VAL 0xDD302014
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#define MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_SRAM_CMP 0xDD302015
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#define MV_DDR3_TRAINING_ERR_PBS_SHIFT_QDS_MAX_VAL 0xDD302016
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#define MV_DDR3_TRAINING_ERR_RD_LVL_RL_PATTERN 0xDD302017
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#define MV_DDR3_TRAINING_ERR_RD_LVL_RL_PUP_UNLOCK 0xDD302018
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#define MV_DDR3_TRAINING_ERR_RD_LVL_PUP_UNLOCK 0xDD302019
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#define MV_DDR3_TRAINING_ERR_WR_LVL_SW 0xDD302020
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#define MV_DDR3_TRAINING_ERR_PRBS_RX 0xDD302021
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#define MV_DDR3_TRAINING_ERR_DQS_RX 0xDD302022
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#define MV_DDR3_TRAINING_ERR_PRBS_TX 0xDD302023
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#define MV_DDR3_TRAINING_ERR_DQS_TX 0xDD302024
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/*
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* DRAM information structure
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*/
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typedef struct dram_info {
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u32 num_cs;
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u32 cs_ena;
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u32 num_of_std_pups; /* Q value = ddrWidth/8 - Without ECC!! */
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u32 num_of_total_pups; /* numOfStdPups + eccEna */
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u32 target_frequency; /* DDR Frequency */
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u32 ddr_width; /* 32/64 Bit or 16/32 Bit */
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u32 ecc_ena; /* 0/1 */
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u32 wl_val[MAX_CS][MAX_PUP_NUM][7];
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u32 rl_val[MAX_CS][MAX_PUP_NUM][7];
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u32 rl_max_phase;
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u32 rl_min_phase;
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u32 wl_max_phase;
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u32 wl_min_phase;
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u32 rd_smpl_dly;
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u32 rd_rdy_dly;
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u32 cl;
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u32 cwl;
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u32 mode_2t;
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int rl400_bug;
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int multi_cs_mr_support;
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int reg_dimm;
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} MV_DRAM_INFO;
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enum training_modes {
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DQS_WR_MODE,
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WL_MODE_,
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RL_MODE_,
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DQS_RD_MODE,
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PBS_TX_DM_MODE,
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PBS_TX_MODE,
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PBS_RX_MODE,
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MAX_TRAINING_MODE,
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};
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typedef struct dram_training_init {
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u32 reg_addr;
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u32 reg_value;
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} MV_DRAM_TRAINING_INIT;
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typedef struct dram_mv_init {
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u32 reg_addr;
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u32 reg_value;
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} MV_DRAM_MC_INIT;
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/* Board/Soc revisions define */
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enum board_rev {
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Z1,
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Z1_PCAC,
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Z1_RD_SLED,
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A0,
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A0_AMC
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};
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typedef struct dram_modes {
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char *mode_name;
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u8 cpu_freq;
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u8 fab_freq;
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u8 chip_id;
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int chip_board_rev;
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MV_DRAM_MC_INIT *regs;
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MV_DRAM_TRAINING_INIT *vals;
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} MV_DRAM_MODES;
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/*
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* Function Declarations
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*/
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u32 cache_inv(u32 addr);
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void flush_l1_v7(u32 line);
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void flush_l1_v6(u32 line);
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u32 ddr3_cl_to_valid_cl(u32 cl);
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u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl);
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void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay);
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u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup);
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int ddr3_sdram_pbs_compare(MV_DRAM_INFO *dram_info, u32 pup_locked, int is_tx,
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u32 pbs_pattern_idx, u32 pbs_curr_val,
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u32 pbs_lock_val, u32 *skew_array,
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u8 *unlock_pup_dq_array, u32 ecc);
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int ddr3_sdram_dqs_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
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u32 *new_locked_pup, u32 *pattern,
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u32 pattern_len, u32 sdram_offset, int write,
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int mask, u32 *mask_pattern, int b_special_compare);
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int ddr3_sdram_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
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u32 *new_locked_pup, u32 *pattern, u32 pattern_len,
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u32 sdram_offset, int write, int mask,
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u32 *mask_pattern, int b_special_compare);
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int ddr3_sdram_direct_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
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u32 *new_locked_pup, u32 *pattern,
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u32 pattern_len, u32 sdram_offset, int write,
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int mask, u32 *mask_pattern);
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int ddr3_sdram_dm_compare(MV_DRAM_INFO *dram_info, u32 unlock_pup,
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u32 *new_locked_pup, u32 *pattern,
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u32 sdram_offset);
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int ddr3_dram_sram_read(u32 src, u32 dst, u32 len);
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int ddr3_load_patterns(MV_DRAM_INFO *dram_info, int resume);
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int ddr3_read_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info);
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int ddr3_read_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
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int ddr3_write_leveling_hw(u32 freq, MV_DRAM_INFO *dram_info);
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int ddr3_write_leveling_sw(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
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int ddr3_write_leveling_hw_reg_dimm(u32 freq, MV_DRAM_INFO *dram_info);
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int ddr3_wl_supplement(MV_DRAM_INFO *dram_info);
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int ddr3_dfs_high_2_low(u32 freq, MV_DRAM_INFO *dram_info);
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int ddr3_dfs_low_2_high(u32 freq, int ratio_2to1, MV_DRAM_INFO *dram_info);
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int ddr3_pbs_tx(MV_DRAM_INFO *dram_info);
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int ddr3_pbs_rx(MV_DRAM_INFO *dram_info);
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int ddr3_load_pbs_patterns(MV_DRAM_INFO *dram_info);
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int ddr3_dqs_centralization_rx(MV_DRAM_INFO *dram_info);
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int ddr3_dqs_centralization_tx(MV_DRAM_INFO *dram_info);
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int ddr3_load_dqs_patterns(MV_DRAM_INFO *dram_info);
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void ddr3_static_training_init(void);
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u8 ddr3_get_eprom_fabric(void);
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void ddr3_set_performance_params(MV_DRAM_INFO *dram_info);
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int ddr3_dram_sram_burst(u32 src, u32 dst, u32 len);
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void ddr3_save_training(MV_DRAM_INFO *dram_info);
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int ddr3_read_training_results(void);
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int ddr3_training_suspend_resume(MV_DRAM_INFO *dram_info);
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int ddr3_get_min_max_read_sample_delay(u32 cs_enable, u32 reg, u32 *min,
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u32 *max, u32 *cs_max);
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int ddr3_get_min_max_rl_phase(MV_DRAM_INFO *dram_info, u32 *min, u32 *max,
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u32 cs);
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int ddr3_odt_activate(int activate);
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int ddr3_odt_read_dynamic_config(MV_DRAM_INFO *dram_info);
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void ddr3_print_freq(u32 freq);
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void ddr3_reset_phy_read_fifo(void);
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#endif /* __DDR3_TRAINING_H */
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