mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-13 14:53:06 +00:00
b7f2bbfff6
The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
375 lines
8.7 KiB
ArmAsm
375 lines
8.7 KiB
ArmAsm
/*
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* (C) Copyright 2014-2015 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Extracted from armv8/start.S
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/gic.h>
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#include <asm/macro.h>
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#ifdef CONFIG_MP
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#include <asm/arch/mp.h>
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#endif
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ENTRY(lowlevel_init)
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mov x29, lr /* Save LR */
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#ifdef CONFIG_FSL_LSCH3
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/* Set Wuo bit for RN-I 20 */
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#ifdef CONFIG_LS2080A
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ldr x0, =CCI_AUX_CONTROL_BASE(20)
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ldr x1, =0x00000010
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bl ccn504_set_aux
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#endif
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/* Add fully-coherent masters to DVM domain */
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ldr x0, =CCI_MN_BASE
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ldr x1, =CCI_MN_RNF_NODEID_LIST
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ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET
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bl ccn504_add_masters_to_dvm
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/* Set all RN-I ports to QoS of 15 */
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ldr x0, =CCI_S0_QOS_CONTROL_BASE(0)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S1_QOS_CONTROL_BASE(0)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(0)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S0_QOS_CONTROL_BASE(2)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S1_QOS_CONTROL_BASE(2)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(2)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S0_QOS_CONTROL_BASE(6)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S1_QOS_CONTROL_BASE(6)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(6)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S0_QOS_CONTROL_BASE(12)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S1_QOS_CONTROL_BASE(12)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(12)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S0_QOS_CONTROL_BASE(16)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S1_QOS_CONTROL_BASE(16)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(16)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S0_QOS_CONTROL_BASE(20)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S1_QOS_CONTROL_BASE(20)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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#endif
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#ifdef SMMU_BASE
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/* Set the SMMU page size in the sACR register */
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ldr x1, =SMMU_BASE
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ldr w0, [x1, #0x10]
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orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
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str w0, [x1, #0x10]
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#endif
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/* Initialize GIC Secure Bank Status */
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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branch_if_slave x0, 1f
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ldr x0, =GICD_BASE
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bl gic_init_secure
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1:
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#ifdef CONFIG_GICV3
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ldr x0, =GICR_BASE
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bl gic_init_secure_percpu
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#elif defined(CONFIG_GICV2)
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ldr x0, =GICD_BASE
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ldr x1, =GICC_BASE
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bl gic_init_secure_percpu
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#endif
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#endif
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branch_if_master x0, x1, 2f
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#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
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ldr x0, =secondary_boot_func
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blr x0
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#endif
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2:
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#ifdef CONFIG_FSL_TZPC_BP147
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/* Set Non Secure access for all devices protected via TZPC */
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ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
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orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
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str w0, [x1]
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isb
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dsb sy
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#endif
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#ifdef CONFIG_FSL_TZASC_400
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/* Set TZASC so that:
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* a. We use only Region0 whose global secure write/read is EN
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* b. We use only Region0 whose NSAID write/read is EN
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*
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* NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
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* placeholders.
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*/
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ldr x1, =TZASC_GATE_KEEPER(0)
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ldr x0, [x1] /* Filter 0 Gate Keeper Register */
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orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */
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str x0, [x1]
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ldr x1, =TZASC_GATE_KEEPER(1)
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ldr x0, [x1] /* Filter 0 Gate Keeper Register */
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orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */
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str x0, [x1]
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ldr x1, =TZASC_REGION_ATTRIBUTES_0(0)
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ldr x0, [x1] /* Region-0 Attributes Register */
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orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */
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orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */
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str x0, [x1]
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ldr x1, =TZASC_REGION_ATTRIBUTES_0(1)
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ldr x0, [x1] /* Region-1 Attributes Register */
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orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */
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orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */
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str x0, [x1]
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ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
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ldr w0, [x1] /* Region-0 Access Register */
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mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
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str w0, [x1]
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ldr x1, =TZASC_REGION_ID_ACCESS_0(1)
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ldr w0, [x1] /* Region-1 Attributes Register */
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mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
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str w0, [x1]
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isb
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dsb sy
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#endif
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mov lr, x29 /* Restore LR */
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ret
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ENDPROC(lowlevel_init)
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#ifdef CONFIG_FSL_LSCH3
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hnf_pstate_poll:
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/* x0 has the desired status, return 0 for success, 1 for timeout
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* clobber x1, x2, x3, x4, x6, x7
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*/
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mov x1, x0
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mov x7, #0 /* flag for timeout */
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mrs x3, cntpct_el0 /* read timer */
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add x3, x3, #1200 /* timeout after 100 microseconds */
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mov x0, #0x18
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movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */
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mov w6, #8 /* HN-F node count */
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1:
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ldr x2, [x0]
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cmp x2, x1 /* check status */
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b.eq 2f
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mrs x4, cntpct_el0
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cmp x4, x3
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b.ls 1b
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mov x7, #1 /* timeout */
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b 3f
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2:
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add x0, x0, #0x10000 /* move to next node */
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subs w6, w6, #1
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cbnz w6, 1b
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3:
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mov x0, x7
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ret
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hnf_set_pstate:
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/* x0 has the desired state, clobber x1, x2, x6 */
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mov x1, x0
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/* power state to SFONLY */
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mov w6, #8 /* HN-F node count */
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mov x0, #0x10
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movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */
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1: /* set pstate to sfonly */
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ldr x2, [x0]
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and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
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orr x2, x2, x1
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str x2, [x0]
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add x0, x0, #0x10000 /* move to next node */
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subs w6, w6, #1
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cbnz w6, 1b
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ret
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ENTRY(__asm_flush_l3_cache)
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/*
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* Return status in x0
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* success 0
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* tmeout 1 for setting SFONLY, 2 for FAM, 3 for both
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*/
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mov x29, lr
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mov x8, #0
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dsb sy
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mov x0, #0x1 /* HNFPSTAT_SFONLY */
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bl hnf_set_pstate
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mov x0, #0x4 /* SFONLY status */
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bl hnf_pstate_poll
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cbz x0, 1f
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mov x8, #1 /* timeout */
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1:
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dsb sy
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mov x0, #0x3 /* HNFPSTAT_FAM */
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bl hnf_set_pstate
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mov x0, #0xc /* FAM status */
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bl hnf_pstate_poll
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cbz x0, 1f
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add x8, x8, #0x2
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1:
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mov x0, x8
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mov lr, x29
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ret
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ENDPROC(__asm_flush_l3_cache)
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#endif
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#ifdef CONFIG_MP
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/* Keep literals not used by the secondary boot code outside it */
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.ltorg
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/* Using 64 bit alignment since the spin table is accessed as data */
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.align 4
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.global secondary_boot_code
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/* Secondary Boot Code starts here */
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secondary_boot_code:
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.global __spin_table
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__spin_table:
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.space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
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.align 2
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ENTRY(secondary_boot_func)
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/*
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* MPIDR_EL1 Fields:
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* MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
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* MPIDR[7:2] = AFF0_RES
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* MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
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* MPIDR[23:16] = AFF2_CLUSTERID
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* MPIDR[24] = MT
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* MPIDR[29:25] = RES0
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* MPIDR[30] = U
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* MPIDR[31] = ME
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* MPIDR[39:32] = AFF3
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*
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* Linear Processor ID (LPID) calculation from MPIDR_EL1:
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* (We only use AFF0_CPUID and AFF1_CLUSTERID for now
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* until AFF2_CLUSTERID and AFF3 have non-zero values)
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*
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* LPID = MPIDR[15:8] | MPIDR[1:0]
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*/
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mrs x0, mpidr_el1
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ubfm x1, x0, #8, #15
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ubfm x2, x0, #0, #1
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orr x10, x2, x1, lsl #2 /* x10 has LPID */
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ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
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/*
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* offset of the spin table element for this core from start of spin
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* table (each elem is padded to 64 bytes)
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*/
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lsl x1, x10, #6
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ldr x0, =__spin_table
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/* physical address of this cpus spin table element */
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add x11, x1, x0
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ldr x0, =__real_cntfrq
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ldr x0, [x0]
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msr cntfrq_el0, x0 /* set with real frequency */
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str x9, [x11, #16] /* LPID */
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mov x4, #1
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str x4, [x11, #8] /* STATUS */
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dsb sy
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#if defined(CONFIG_GICV3)
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gic_wait_for_interrupt_m x0
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#elif defined(CONFIG_GICV2)
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ldr x0, =GICC_BASE
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gic_wait_for_interrupt_m x0, w1
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#endif
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bl secondary_switch_to_el2
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#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
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bl secondary_switch_to_el1
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#endif
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slave_cpu:
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wfe
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ldr x0, [x11]
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cbz x0, slave_cpu
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#ifndef CONFIG_ARMV8_SWITCH_TO_EL1
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mrs x1, sctlr_el2
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#else
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mrs x1, sctlr_el1
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#endif
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tbz x1, #25, cpu_is_le
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rev x0, x0 /* BE to LE conversion */
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cpu_is_le:
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br x0 /* branch to the given address */
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ENDPROC(secondary_boot_func)
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ENTRY(secondary_switch_to_el2)
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switch_el x0, 1f, 0f, 0f
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0: ret
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1: armv8_switch_to_el2_m x0
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ENDPROC(secondary_switch_to_el2)
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ENTRY(secondary_switch_to_el1)
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switch_el x0, 0f, 1f, 0f
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0: ret
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1: armv8_switch_to_el1_m x0, x1
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ENDPROC(secondary_switch_to_el1)
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/* Ensure that the literals used by the secondary boot code are
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* assembled within it (this is required so that we can protect
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* this area with a single memreserve region
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*/
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.ltorg
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/* 64 bit alignment for elements accessed as data */
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.align 4
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.global __real_cntfrq
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__real_cntfrq:
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.quad COUNTER_FREQUENCY
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.globl __secondary_boot_code_size
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.type __secondary_boot_code_size, %object
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/* Secondary Boot Code ends here */
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__secondary_boot_code_size:
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.quad .-secondary_boot_code
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#endif
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