mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-28 18:32:08 +00:00
3408d96e6c
This commit removes the following unused symbols: CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_SIZE CONFIG_SYS_PAXE_BASE CONFIG_SYS_PCCNT CONFIG_SYS_PCDAT CONFIG_SYS_PCDDR CONFIG_SYS_PCI1_ADDR CONFIG_SYS_PCI2_ADDR CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_SIZE CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_SIZE CONFIG_SYS_PCIE3_ADDR CONFIG_SYS_PCIE4_ADDR CONFIG_SYS_PCIE3_IO_PHYS CONFIG_SYS_PCIE3_IO_VIRT CONFIG_SYS_PCIE4_IO_PHYS CONFIG_SYS_PCIE4_IO_VIRT CONFIG_SYS_PLL_SETTLING_TIME CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_SP_CENA_SIZE CONFIG_SYS_RCAR_I2C0_BASE CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C3_BASE CONFIG_SYS_SATA CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_SGMII_REFCLK_MHZ CONFIG_SYS_SGMII_LINERATE_MHZ CONFIG_SYS_SGMII_RATESCALE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI1_BASE CONFIG_SYS_SH_SDHI2_BASE CONFIG_SYS_SH_SDHI3_BASE CONFIG_SYS_SPI_ST_ENABLE_WP_PIN CONFIG_SYS_SPI_U_BOOT_SIZE CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT CONFIG_SYS_VCXK_BASE CONFIG_SYS_VCXK_DEFAULT_LINEALIGN CONFIG_SYS_VCXK_DOUBLEBUFFERED CONFIG_SYS_VCXK_ENABLE_DDR CONFIG_SYS_VCXK_ENABLE_PIN CONFIG_SYS_VCXK_ENABLE_PORT CONFIG_SYS_VCXK_INVERT_DDR CONFIG_SYS_VCXK_INVERT_PIN CONFIG_SYS_VCXK_INVERT_PORT CONFIG_SYS_VCXK_REQUEST_DDR CONFIG_SYS_VCXK_REQUEST_PIN CONFIG_SYS_VCXK_REQUEST_PORT CONFIG_SYS_VSC7385_BR_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
73 lines
2.3 KiB
C
73 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright 2017, 2021 NXP
|
|
*/
|
|
|
|
#ifndef __LS1012A2G5RDB_H__
|
|
#define __LS1012A2G5RDB_H__
|
|
|
|
#include "ls1012a_common.h"
|
|
|
|
/* DDR */
|
|
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
|
|
|
|
#undef CONFIG_EXTRA_ENV_SETTINGS
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"verify=no\0" \
|
|
"initrd_high=0xffffffffffffffff\0" \
|
|
"kernel_addr=0x01000000\0" \
|
|
"kernelheader_addr=0x800000\0" \
|
|
"scriptaddr=0x80000000\0" \
|
|
"scripthdraddr=0x80080000\0" \
|
|
"fdtheader_addr_r=0x80100000\0" \
|
|
"kernelheader_addr_r=0x80200000\0" \
|
|
"kernel_addr_r=0x81000000\0" \
|
|
"fdt_addr_r=0x90000000\0" \
|
|
"load_addr=0xa0000000\0" \
|
|
"kernel_size=0x2800000\0" \
|
|
"kernelheader_size=0x40000\0" \
|
|
"bootm_size=0x10000000\0" \
|
|
"console=ttyS0,115200\0" \
|
|
BOOTENV \
|
|
"boot_scripts=ls1012ardb_boot.scr\0" \
|
|
"boot_script_hdr=hdr_ls1012ardb_bs.out\0" \
|
|
"scan_dev_for_boot_part=" \
|
|
"part list ${devtype} ${devnum} devplist; " \
|
|
"env exists devplist || setenv devplist 1; " \
|
|
"for distro_bootpart in ${devplist}; do " \
|
|
"if fstype ${devtype} " \
|
|
"${devnum}:${distro_bootpart} " \
|
|
"bootfstype; then " \
|
|
"run scan_dev_for_boot; " \
|
|
"fi; " \
|
|
"done\0" \
|
|
"boot_a_script=" \
|
|
"load ${devtype} ${devnum}:${distro_bootpart} " \
|
|
"${scriptaddr} ${prefix}${script}; " \
|
|
"env exists secureboot && load ${devtype} " \
|
|
"${devnum}:${distro_bootpart} " \
|
|
"${scripthdraddr} ${prefix}${boot_script_hdr} " \
|
|
"&& esbc_validate ${scripthdraddr};" \
|
|
"source ${scriptaddr}\0" \
|
|
"installer=load mmc 0:2 $load_addr " \
|
|
"/flex_installer_arm64.itb; " \
|
|
"bootm $load_addr#$board\0" \
|
|
"qspi_bootcmd=echo Trying load from qspi..;" \
|
|
"sf probe && sf read $load_addr " \
|
|
"$kernel_addr $kernel_size; env exists secureboot " \
|
|
"&& sf read $kernelheader_addr_r $kernelheader_addr " \
|
|
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
|
|
"bootm $load_addr#$board\0"
|
|
|
|
#ifdef CONFIG_TFABOOT
|
|
#undef QSPI_NOR_BOOTCOMMAND
|
|
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
|
|
"env exists secureboot && esbc_halt;"
|
|
#endif
|
|
|
|
#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
|
|
#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
|
|
|
|
#include <asm/fsl_secure_boot.h>
|
|
|
|
#endif /* __LS1012A2G5RDB_H__ */
|