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https://github.com/AsahiLinux/u-boot
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3408d96e6c
This commit removes the following unused symbols: CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_SIZE CONFIG_SYS_PAXE_BASE CONFIG_SYS_PCCNT CONFIG_SYS_PCDAT CONFIG_SYS_PCDDR CONFIG_SYS_PCI1_ADDR CONFIG_SYS_PCI2_ADDR CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_SIZE CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_SIZE CONFIG_SYS_PCIE3_ADDR CONFIG_SYS_PCIE4_ADDR CONFIG_SYS_PCIE3_IO_PHYS CONFIG_SYS_PCIE3_IO_VIRT CONFIG_SYS_PCIE4_IO_PHYS CONFIG_SYS_PCIE4_IO_VIRT CONFIG_SYS_PLL_SETTLING_TIME CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_SP_CENA_SIZE CONFIG_SYS_RCAR_I2C0_BASE CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C3_BASE CONFIG_SYS_SATA CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_SGMII_REFCLK_MHZ CONFIG_SYS_SGMII_LINERATE_MHZ CONFIG_SYS_SGMII_RATESCALE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI1_BASE CONFIG_SYS_SH_SDHI2_BASE CONFIG_SYS_SH_SDHI3_BASE CONFIG_SYS_SPI_ST_ENABLE_WP_PIN CONFIG_SYS_SPI_U_BOOT_SIZE CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT CONFIG_SYS_VCXK_BASE CONFIG_SYS_VCXK_DEFAULT_LINEALIGN CONFIG_SYS_VCXK_DOUBLEBUFFERED CONFIG_SYS_VCXK_ENABLE_DDR CONFIG_SYS_VCXK_ENABLE_PIN CONFIG_SYS_VCXK_ENABLE_PORT CONFIG_SYS_VCXK_INVERT_DDR CONFIG_SYS_VCXK_INVERT_PIN CONFIG_SYS_VCXK_INVERT_PORT CONFIG_SYS_VCXK_REQUEST_DDR CONFIG_SYS_VCXK_REQUEST_PIN CONFIG_SYS_VCXK_REQUEST_PORT CONFIG_SYS_VSC7385_BR_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
33 lines
813 B
C
33 lines
813 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* arch/arm/include/asm/arch-rmobile/r8a7790.h
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*
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* Copyright (C) 2013,2014 Renesas Electronics Corporation
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*/
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#ifndef __ASM_ARCH_R8A7790_H
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#define __ASM_ARCH_R8A7790_H
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#include "rcar-base.h"
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/* Module stop control/status register bits */
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#define MSTP0_BITS 0x00640801
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#define MSTP1_BITS 0xDB6E9BDF
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#define MSTP2_BITS 0x300DA1FC
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#define MSTP3_BITS 0xF08CF831
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#define MSTP4_BITS 0x80000184
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#define MSTP5_BITS 0x44C00046
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#define MSTP7_BITS 0x07F30718
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#define MSTP8_BITS 0x01F0FF84
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#define MSTP9_BITS 0xF5979FCF
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#define MSTP10_BITS 0xFFFEFFE0
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#define MSTP11_BITS 0x00000000
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/* SDHI */
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#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
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#define R8A7790_CUT_ES2X 2
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#define IS_R8A7790_ES2() \
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(rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
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#endif /* __ASM_ARCH_R8A7790_H */
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