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0296ec364d
Add all Clock Pulse Generator Core Clock Outputs for the
Renesas R-Car V4H (R8A779G0) SoC from Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tho Vu <tho.vu.wh@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Update to linux next 20230228 state]
90 lines
2.7 KiB
C
90 lines
2.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2022 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a779g0 CPG Core Clocks */
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#define R8A779G0_CLK_ZX 0
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#define R8A779G0_CLK_ZS 1
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#define R8A779G0_CLK_ZT 2
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#define R8A779G0_CLK_ZTR 3
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#define R8A779G0_CLK_S0D2 4
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#define R8A779G0_CLK_S0D3 5
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#define R8A779G0_CLK_S0D4 6
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#define R8A779G0_CLK_S0D1_VIO 7
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#define R8A779G0_CLK_S0D2_VIO 8
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#define R8A779G0_CLK_S0D4_VIO 9
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#define R8A779G0_CLK_S0D8_VIO 10
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#define R8A779G0_CLK_S0D1_VC 11
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#define R8A779G0_CLK_S0D2_VC 12
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#define R8A779G0_CLK_S0D4_VC 13
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#define R8A779G0_CLK_S0D2_MM 14
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#define R8A779G0_CLK_S0D4_MM 15
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#define R8A779G0_CLK_S0D2_U3DG 16
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#define R8A779G0_CLK_S0D4_U3DG 17
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#define R8A779G0_CLK_S0D2_RT 18
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#define R8A779G0_CLK_S0D3_RT 19
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#define R8A779G0_CLK_S0D4_RT 20
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#define R8A779G0_CLK_S0D6_RT 21
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#define R8A779G0_CLK_S0D24_RT 22
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#define R8A779G0_CLK_S0D2_PER 23
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#define R8A779G0_CLK_S0D3_PER 24
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#define R8A779G0_CLK_S0D4_PER 25
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#define R8A779G0_CLK_S0D6_PER 26
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#define R8A779G0_CLK_S0D12_PER 27
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#define R8A779G0_CLK_S0D24_PER 28
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#define R8A779G0_CLK_S0D1_HSC 29
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#define R8A779G0_CLK_S0D2_HSC 30
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#define R8A779G0_CLK_S0D4_HSC 31
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#define R8A779G0_CLK_S0D2_CC 32
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#define R8A779G0_CLK_SVD1_IR 33
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#define R8A779G0_CLK_SVD2_IR 34
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#define R8A779G0_CLK_SVD1_VIP 35
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#define R8A779G0_CLK_SVD2_VIP 36
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#define R8A779G0_CLK_CL 37
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#define R8A779G0_CLK_CL16M 38
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#define R8A779G0_CLK_CL16M_MM 39
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#define R8A779G0_CLK_CL16M_RT 40
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#define R8A779G0_CLK_CL16M_PER 41
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#define R8A779G0_CLK_CL16M_HSC 42
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#define R8A779G0_CLK_Z0 43
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#define R8A779G0_CLK_ZB3 44
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#define R8A779G0_CLK_ZB3D2 45
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#define R8A779G0_CLK_ZB3D4 46
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#define R8A779G0_CLK_ZG 47
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#define R8A779G0_CLK_SD0H 48
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#define R8A779G0_CLK_SD0 49
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#define R8A779G0_CLK_RPC 50
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#define R8A779G0_CLK_RPCD2 51
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#define R8A779G0_CLK_MSO 52
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#define R8A779G0_CLK_CANFD 53
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#define R8A779G0_CLK_CSI 54
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#define R8A779G0_CLK_FRAY 55
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#define R8A779G0_CLK_IPC 56
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#define R8A779G0_CLK_SASYNCRT 57
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#define R8A779G0_CLK_SASYNCPERD1 58
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#define R8A779G0_CLK_SASYNCPERD2 59
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#define R8A779G0_CLK_SASYNCPERD4 60
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#define R8A779G0_CLK_VIOBUS 61
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#define R8A779G0_CLK_VIOBUSD2 62
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#define R8A779G0_CLK_VCBUS 63
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#define R8A779G0_CLK_VCBUSD2 64
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#define R8A779G0_CLK_DSIEXT 65
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#define R8A779G0_CLK_DSIREF 66
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#define R8A779G0_CLK_ADGH 67
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#define R8A779G0_CLK_OSC 68
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#define R8A779G0_CLK_ZR0 69
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#define R8A779G0_CLK_ZR1 70
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#define R8A779G0_CLK_ZR2 71
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#define R8A779G0_CLK_IMPA 72
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#define R8A779G0_CLK_IMPAD4 73
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#define R8A779G0_CLK_CPEX 74
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#define R8A779G0_CLK_CBFUSA 75
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#define R8A779G0_CLK_R 76
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#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */
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