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b03a466d6c
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require that we initialize the SERDES registers if the lanes are configured for PCIe. Additionally these devices PCIe controller do not support ASPM and we have to explicitly disable it. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
111 lines
3.4 KiB
C
111 lines
3.4 KiB
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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typedef struct serdes_85xx {
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u32 srdscr0; /* 0x00 - SRDS Control Register 0 */
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u32 srdscr1; /* 0x04 - SRDS Control Register 1 */
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u32 srdscr2; /* 0x08 - SRDS Control Register 2 */
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u32 srdscr3; /* 0x0C - SRDS Control Register 3 */
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u32 srdscr4; /* 0x10 - SRDS Control Register 4 */
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} serdes_85xx_t;
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#define FSL_SRDSCR3_EIC0(x) (((x) & 0x1f) << 8)
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#define FSL_SRDSCR3_EIC0_MASK FSL_SRDSCR3_EIC0(0x1f)
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#define FSL_SRDSCR3_EIC1(x) (((x) & 0x1f) << 0)
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#define FSL_SRDSCR3_EIC1_MASK FSL_SRDSCR3_EIC1(0x1f)
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#define FSL_SRDSCR4_EIC2(x) (((x) & 0x1f) << 8)
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#define FSL_SRDSCR4_EIC2_MASK FSL_SRDSCR4_EIC2(0x1f)
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#define FSL_SRDSCR4_EIC3(x) (((x) & 0x1f) << 0)
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#define FSL_SRDSCR4_EIC3_MASK FSL_SRDSCR4_EIC3(0x1f)
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#define EIC_PCIE 0x13
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#define EIC_SGMII 0x04
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#define SRDS1_MAX_LANES 4
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static u32 serdes1_prtcl_map;
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static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
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[0x0] = {PCIE1, NONE, NONE, NONE},
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[0x6] = {PCIE1, PCIE1, PCIE1, PCIE1},
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[0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3},
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[0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3},
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};
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int is_serdes_configured(enum srds_prtcl prtcl)
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{
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return (1 << prtcl) & serdes1_prtcl_map;
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}
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void fsl_serdes_init(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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serdes_85xx_t *serdes = (void *)CONFIG_SYS_MPC85xx_SERDES1_ADDR;
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u32 pordevsr = in_be32(&gur->pordevsr);
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u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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int lane;
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u32 mask, val;
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debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
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if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
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printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
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return;
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}
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for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
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serdes1_prtcl_map |= (1 << lane_prtcl);
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}
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/* Init SERDES Receiver electrical idle detection control for PCIe */
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/* Lane 0 is always PCIe 1 */
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mask = FSL_SRDSCR3_EIC0_MASK;
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val = FSL_SRDSCR3_EIC0(EIC_PCIE);
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/* Lane 1 */
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if ((serdes1_cfg_tbl[srds_cfg][1] == PCIE1) ||
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(serdes1_cfg_tbl[srds_cfg][1] == PCIE2)) {
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mask |= FSL_SRDSCR3_EIC1_MASK;
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val |= FSL_SRDSCR3_EIC1(EIC_PCIE);
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}
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/* Handle lanes 0 & 1 */
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clrsetbits_be32(&serdes->srdscr3, mask, val);
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/* Handle lanes 2 & 3 */
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if (srds_cfg == 0x6) {
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mask = FSL_SRDSCR4_EIC2_MASK | FSL_SRDSCR4_EIC3_MASK;
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val = FSL_SRDSCR4_EIC2(EIC_PCIE) | FSL_SRDSCR4_EIC3(EIC_PCIE);
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clrsetbits_be32(&serdes->srdscr4, mask, val);
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}
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/* 100 ms delay */
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udelay(100000);
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}
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