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7d9c6f1781
The i.MXRT11 series has different offsets for IOCR_MUX, it also can address 64MiB of SDRAM so add a macro for that. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
101 lines
2.4 KiB
C
101 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2019
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* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
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*/
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#ifndef DT_BINDINGS_IMXRT_SDRAM_H
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#define DT_BINDINGS_IMXRT_SDRAM_H
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#define MEM_SIZE_4K 0x00
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#define MEM_SIZE_8K 0x01
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#define MEM_SIZE_16K 0x02
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#define MEM_SIZE_32K 0x03
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#define MEM_SIZE_64K 0x04
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#define MEM_SIZE_128K 0x05
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#define MEM_SIZE_256K 0x06
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#define MEM_SIZE_512K 0x07
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#define MEM_SIZE_1M 0x08
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#define MEM_SIZE_2M 0x09
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#define MEM_SIZE_4M 0x0A
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#define MEM_SIZE_8M 0x0B
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#define MEM_SIZE_16M 0x0C
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#define MEM_SIZE_32M 0x0D
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#define MEM_SIZE_64M 0x0E
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#define MEM_SIZE_128M 0x0F
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#define MEM_SIZE_256M 0x10
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#define MEM_SIZE_512M 0x11
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#define MEM_SIZE_1G 0x12
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#define MEM_SIZE_2G 0x13
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#define MEM_SIZE_4G 0x14
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#define MUX_A8_SDRAM_A8 0x0
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#define MUX_A8_NAND_CE 0x1
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#define MUX_A8_NOR_CE 0x2
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#define MUX_A8_PSRAM_CE 0x3
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#define MUX_A8_DBI_CSX 0x4
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#define MUX_CSX0_NOR_PSRAM_A24 0x0
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#define MUX_CSX0_SDRAM_CS1 0x1
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#define MUX_CSX0_SDRAM_CS2 0x2
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#define MUX_CSX0_SDRAM_CS3 0x3
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#define MUX_CSX0_NAND_CE 0x4
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#define MUX_CSX0_NOR_CE 0x5
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#define MUX_CSX0_PSRAM_CE 0x6
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#define MUX_CSX0_DBI_CSX 0x7
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#define MUX_CSX1_NOR_PSRAM_A25 0x0
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#define MUX_CSX1_SDRAM_CS1 0x1
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#define MUX_CSX1_SDRAM_CS2 0x2
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#define MUX_CSX1_SDRAM_CS3 0x3
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#define MUX_CSX1_NAND_CE 0x4
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#define MUX_CSX1_NOR_CE 0x5
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#define MUX_CSX1_PSRAM_CE 0x6
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#define MUX_CSX1_DBI_CSX 0x7
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#define MUX_CSX2_NOR_PSRAM_A26 0x0
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#define MUX_CSX2_SDRAM_CS1 0x1
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#define MUX_CSX2_SDRAM_CS2 0x2
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#define MUX_CSX2_SDRAM_CS3 0x3
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#define MUX_CSX2_NAND_CE 0x4
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#define MUX_CSX2_NOR_CE 0x5
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#define MUX_CSX2_PSRAM_CE 0x6
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#define MUX_CSX2_DBI_CSX 0x7
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#define MUX_CSX3_NOR_PSRAM_A27 0x0
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#define MUX_CSX3_SDRAM_CS1 0x1
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#define MUX_CSX3_SDRAM_CS2 0x2
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#define MUX_CSX3_SDRAM_CS3 0x3
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#define MUX_CSX3_NAND_CE 0x4
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#define MUX_CSX3_NOR_CE 0x5
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#define MUX_CSX3_PSRAM_CE 0x6
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#define MUX_CSX3_DBI_CSX 0x7
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#define MUX_RDY_NAND_RDY_WAIT 0x0
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#define MUX_RDY_SDRAM_CS1 0x1
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#define MUX_RDY_SDRAM_CS2 0x2
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#define MUX_RDY_SDRAM_CS3 0x3
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#define MUX_RDY_NOR_CE 0x4
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#define MUX_RDY_PSRAM_CE 0x5
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#define MUX_RDY_DBI_CSX 0x6
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#define MUX_RDY_NOR_PSRAM_A27 0x7
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#define MEM_WIDTH_8BITS 0x0
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#define MEM_WIDTH_16BITS 0x1
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#define MEM_WIDTH_32BITS 0x2
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#define BL_1 0x0
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#define BL_2 0x1
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#define BL_4 0x2
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#define BL_8 0x3
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#define COL_12BITS 0x0
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#define COL_11BITS 0x1
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#define COL_10BITS 0x2
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#define COL_9BITS 0x3
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#define CL_1 0x0
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#define CL_2 0x2
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#define CL_3 0x3
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#endif
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