mirror of
https://github.com/AsahiLinux/u-boot
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012522fef3
Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG, MDHA, SKHA, INTC, and FlexBus structures and definitions in immap_5xxx.h to more unify modules header files. Append DSPI support for m547x_8x. SSI cleanup. Remove USB Host structure from immap_539.h. Apply changes to use FlexBus structures in mcf52x2's cpu_init.c and platform configuration files. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
121 lines
3.9 KiB
C
121 lines
3.9 KiB
C
/*
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* Symmetric Key Hardware Accelerator Memory Map
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*
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* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __SKHA_H__
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#define __SKHA_H__
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typedef struct skha_ctrl {
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u32 mr; /* 0x00 Mode */
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u32 cr; /* 0x04 Control */
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u32 cmr; /* 0x08 Command */
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u32 sr; /* 0x0C Status */
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u32 esr; /* 0x10 Error Status */
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u32 emr; /* 0x14 Error Status Mask Register) */
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u32 ksr; /* 0x18 Key Size */
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u32 dsr; /* 0x1C Data Size */
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u32 in; /* 0x20 Input FIFO */
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u32 out; /* 0x24 Output FIFO */
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u32 res1[2]; /* 0x28 - 0x2F */
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u32 kdr1; /* 0x30 Key Data 1 */
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u32 kdr2; /* 0x34 Key Data 2 */
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u32 kdr3; /* 0x38 Key Data 3 */
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u32 kdr4; /* 0x3C Key Data 4 */
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u32 kdr5; /* 0x40 Key Data 5 */
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u32 kdr6; /* 0x44 Key Data 6 */
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u32 res2[10]; /* 0x48 - 0x6F */
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u32 c1; /* 0x70 Context 1 */
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u32 c2; /* 0x74 Context 2 */
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u32 c3; /* 0x78 Context 3 */
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u32 c4; /* 0x7C Context 4 */
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u32 c5; /* 0x80 Context 5 */
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u32 c6; /* 0x84 Context 6 */
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u32 c7; /* 0x88 Context 7 */
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u32 c8; /* 0x8C Context 8 */
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u32 c9; /* 0x90 Context 9 */
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u32 c10; /* 0x94 Context 10 */
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u32 c11; /* 0x98 Context 11 */
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u32 c12; /* 0x9C Context 12 - 5235, 5271, 5272 */
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} skha_t;
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#ifdef CONFIG_MCF532x
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#define SKHA_MODE_CTRM(x) (((x) & 0x0F) << 9)
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#define SKHA_MODE_CTRM_MASK (0xFFFFE1FF)
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#define SKHA_MODE_DKP (0x00000100)
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#else
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#define SKHA_MODE_CTRM(x) (((x) & 0x0F) << 8)
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#define SKHA_MODE_CTRM_MASK (0xFFFFF0FF)
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#define SKHA_MODE_DKP (0x00000080)
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#endif
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#define SKHA_MODE_CM(x) (((x) & 0x03) << 3)
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#define SKHA_MODE_CM_MASK (0xFFFFFFE7)
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#define SKHA_MODE_DIR (0x00000004)
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#define SKHA_MODE_ALG(x) ((x) & 0x03)
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#define SKHA_MODE_ALG_MASK (0xFFFFFFFC)
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#define SHKA_CR_ODMAL(x) (((x) & 0x3F) << 24)
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#define SHKA_CR_ODMAL_MASK (0xC0FFFFFF)
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#define SHKA_CR_IDMAL(x) (((x) & 0x3F) << 16)
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#define SHKA_CR_IDMAL_MASK (0xFFC0FFFF)
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#define SHKA_CR_END (0x00000008)
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#define SHKA_CR_ODMA (0x00000004)
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#define SHKA_CR_IDMA (0x00000002)
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#define SKHA_CR_IE (0x00000001)
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#define SKHA_CMR_GO (0x00000008)
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#define SKHA_CMR_CI (0x00000004)
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#define SKHA_CMR_RI (0x00000002)
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#define SKHA_CMR_SWR (0x00000001)
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#define SKHA_SR_OFL(x) (((x) & 0xFF) << 24)
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#define SKHA_SR_OFL_MASK (0x00FFFFFF)
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#define SKHA_SR_IFL(x) (((x) & 0xFF) << 16)
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#define SKHA_SR_IFL_MASK (0xFF00FFFF)
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#define SKHA_SR_AESES(x) (((x) & 0x1F) << 11)
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#define SKHA_SR_AESES_MASK (0xFFFF07FF)
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#define SKHA_SR_DESES(x) (((x) & 0x7) << 8)
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#define SKHA_SR_DESES_MASK (0xFFFFF8FF)
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#define SKHA_SR_BUSY (0x00000010)
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#define SKHA_SR_RD (0x00000008)
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#define SKHA_SR_ERR (0x00000004)
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#define SKHA_SR_DONE (0x00000002)
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#define SKHA_SR_INT (0x00000001)
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#define SHKA_ESE_DRL (0x00000800)
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#define SKHA_ESR_KRE (0x00000400)
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#define SKHA_ESR_KPE (0x00000200)
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#define SKHA_ESR_ERE (0x00000100)
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#define SKHA_ESR_RMDP (0x00000080)
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#define SKHA_ESR_KSE (0x00000040)
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#define SKHA_ESR_DSE (0x00000020)
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#define SKHA_ESR_IME (0x00000010)
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#define SKHA_ESR_NEOF (0x00000008)
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#define SKHA_ESR_NEIF (0x00000004)
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#define SKHA_ESR_OFU (0x00000002)
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#define SKHA_ESR_IFO (0x00000001)
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#define SKHA_KSR_SZ(x) ((x) & 0x3F)
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#define SKHA_KSR_SZ_MASK (0xFFFFFFC0)
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#endif /* __SKHA_H__ */
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