Chen-Yu Tsai 328ce7fd50 sunxi: Set PLL lock enable bits for R40 ... According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has an extra "PLL lock control" register in the CCU, which controls whether the individual PLL lock status bits in each PLL's control register work or not. This patch enables it for all the PLLs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>		2017-04-20 13:30:01 +02:00
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asm	sunxi: Set PLL lock enable bits for R40	2017-04-20 13:30:01 +02:00
debug	arm: debug: replace license blocks with SPDX	2014-10-26 22:22:09 +01:00