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https://github.com/AsahiLinux/u-boot
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98ba144ccc
It disables the current map first Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
237 lines
8.2 KiB
C
237 lines
8.2 KiB
C
/*
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* (C) Copyright 2005-2007
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* Samsung Electronics,
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* Kyungmin Park <kyungmin.park@samsung.com>
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*
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* Derived from omap2420
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/omap2420.h>
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#include <asm/io.h>
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#include <asm/arch/bits.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/clocks.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/sys_info.h>
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#include "mem.h"
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/************************************************************
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* sdelay() - simple spin loop. Will be constant time as
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* its generally used in 12MHz bypass conditions only. This
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* is necessary until timers are accessible.
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*
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* not inline to increase chances its in cache when called
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*************************************************************/
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void sdelay(unsigned long loops)
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{
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__asm__("1:\n" "subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0"(loops));
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}
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/********************************************************************
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* prcm_init() - inits clocks for PRCM as defined in clocks.h
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* (config II default).
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* -- called from SRAM, or Flash (using temp SRAM stack).
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********************************************************************/
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void prcm_init(void) { }
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/**************************************************************************
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* make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
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* command line mem=xyz use all memory with out discontigious support
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* compiled in. Could do it at the ATAG, but there really is two banks...
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* Called as part of 2nd phase DDR init.
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**************************************************************************/
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void make_cs1_contiguous(void)
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{
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u32 size, a_add_low, a_add_high;
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size = get_sdr_cs_size(SDRC_CS0_OSET);
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size /= SZ_32M; /* find size to offset CS1 */
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a_add_high = (size & 3) << 8; /* set up low field */
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a_add_low = (size & 0x3C) >> 2; /* set up high field */
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__raw_writel((a_add_high | a_add_low), SDRC_CS_CFG);
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}
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/********************************************************
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* mem_ok() - test used to see if timings are correct
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* for a part. Helps in gussing which part
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* we are currently using.
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*******************************************************/
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u32 mem_ok(void)
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{
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u32 val1, val2;
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u32 pattern = 0x12345678;
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/* clear pos A */
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__raw_writel(0x0, OMAP2420_SDRC_CS0 + 0x400);
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/* pattern to pos B */
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__raw_writel(pattern, OMAP2420_SDRC_CS0);
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/* remove pattern off the bus */
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__raw_writel(0x0, OMAP2420_SDRC_CS0 + 4);
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/* get pos A value */
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val1 = __raw_readl(OMAP2420_SDRC_CS0 + 0x400);
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val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */
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/* see if pos A value changed */
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if ((val1 != 0) || (val2 != pattern))
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return (0);
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else
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return (1);
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}
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/********************************************************
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* sdrc_init() - init the sdrc chip selects CS0 and CS1
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* - early init routines, called from flash or
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* SRAM.
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*******************************************************/
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void sdrc_init(void)
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{
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#define EARLY_INIT 1
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/* only init up first bank here */
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do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT);
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}
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/*************************************************************************
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* do_sdrc_init(): initialize the SDRAM for use.
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* -called from low level code with stack only.
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* -code sets up SDRAM timing and muxing for 2422 or 2420.
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* -optimal settings can be placed here, or redone after i2c
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* inspection of board info
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*
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* This is a bit ugly, but should handle all memory moduels
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* used with the APOLLON. The first time though this code from s_init()
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* we configure the first chip select. Later on we come back and
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* will configure the 2nd chip select if it exists.
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*
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**************************************************************************/
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void do_sdrc_init(u32 offset, u32 early)
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{
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}
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/*****************************************************
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* gpmc_init(): init gpmc bus
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* Init GPMC for x16, MuxMode (SDRAM in x32).
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* This code can only be executed from SRAM or SDRAM.
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*****************************************************/
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void gpmc_init(void)
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{
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u32 mux = 0, mtype, mwidth, rev, tval;
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rev = get_cpu_rev();
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if (rev == CPU_2420_2422_ES1)
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tval = 1;
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else
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tval = 0; /* disable bit switched meaning */
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/* global settings */
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__raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
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__raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
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__raw_writel(tval, GPMC_TIMEOUT_CONTROL); /* timeout disable */
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#ifdef CFG_NAND_BOOT
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/* set nWP, disable limited addr */
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__raw_writel(0x001, GPMC_CONFIG);
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#else
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/* set nWP, disable limited addr */
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__raw_writel(0x111, GPMC_CONFIG);
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#endif
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/* discover bus connection from sysboot */
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if (is_gpmc_muxed() == GPMC_MUXED)
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mux = BIT9;
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mtype = get_gpmc0_type();
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mwidth = get_gpmc0_width();
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/* setup cs0 */
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__raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */
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sdelay(1000);
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#ifdef CFG_NOR_BOOT
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__raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_0);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_0);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_0);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_0);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_0);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_0);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_0);
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#else
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__raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
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GPMC_CONFIG1_0);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);
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#endif
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sdelay(2000);
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/* setup cs1 */
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__raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */
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sdelay(1000);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG1_1, GPMC_CONFIG1_1);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1);
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sdelay(2000);
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/* setup cs2 */
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__raw_writel(0x0, GPMC_CONFIG7_2); /* disable current map */
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sdelay(1000);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
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GPMC_CONFIG1_2);
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/* It's same as cs 0 */
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__raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_2);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_2);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_2);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_2);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_2);
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#ifdef CFG_NOR_BOOT
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__raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_2);
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#else
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__raw_writel(APOLLON_24XX_GPMC_CONFIG7_2, GPMC_CONFIG7_2);
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#endif
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#ifndef CFG_NOR_BOOT
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/* setup cs3 */
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__raw_writel(0, GPMC_CONFIG7_3); /* disable any mapping */
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sdelay(1000);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_3);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_3);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_3);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_3);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_3);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_3);
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__raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_3);
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#endif
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#ifndef ASYNC_NOR
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__raw_writew(0xaa, (APOLLON_CS3_BASE + 0xaaa));
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__raw_writew(0x55, (APOLLON_CS3_BASE + 0x554));
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__raw_writew(0xc0, (APOLLON_CS3_BASE | SYNC_NOR_VALUE));
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#endif
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sdelay(2000);
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}
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