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To clean up reset handling for socfpga gen5, port the DDR driver to DM using UCLASS_RAM and implement proper reset handling. This gets us rid of one ad-hoc call to socfpga_per_reset(). The gen5 driver is implemented in 2 distinct files. One of it (containing the calibration training) is not touched much and is kept at using hard coded addresses since the code grows even more otherwise. SPL is changed from calling hard into the DDR driver code to just probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM driver after that. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
7 lines
247 B
Text
7 lines
247 B
Text
config ALTERA_SDRAM
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bool "SoCFPGA DDR SDRAM driver"
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depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
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select RAM if TARGET_SOCFPGA_GEN5
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select SPL_RAM if TARGET_SOCFPGA_GEN5
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help
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Enable DDR SDRAM controller for the SoCFPGA devices.
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