u-boot/arch/mips/mach-bmips/dram.c
Álvaro Fernández Rojas ee422142f4 MIPS: add initial infrastructure for Broadcom MIPS SoCs
CFE checks CPU Thread in a different way (using register $22):
mfc0	t1, C0_BCM_CONFIG, 3 # $22
li	t2, CP0_CMT_TPID # (1 << 31)
and	t1, t2
bnez	t1, 2f	# if we are running on thread 1, skip init
nop

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00

37 lines
661 B
C

/*
* Copyright (C) 2016 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <ram.h>
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
struct ram_info ram;
struct udevice *dev;
int err;
err = uclass_get_device(UCLASS_RAM, 0, &dev);
if (err) {
debug("DRAM init failed: %d\n", err);
return 0;
}
err = ram_get_info(dev, &ram);
if (err) {
debug("Cannot get DRAM size: %d\n", err);
return 0;
}
debug("SDRAM base=%zx, size=%x\n", ram.base, ram.size);
gd->ram_size = ram.size;
return 0;
}