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https://github.com/AsahiLinux/u-boot
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b528b9377d
The LS1046A processor is built on the QorIQ LS series architecture combining four ARM A72 processor cores with DPAA 1.0 support. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
159 lines
2.5 KiB
C
159 lines
2.5 KiB
C
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_SERDES_H__
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#define __FSL_SERDES_H__
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#include <config.h>
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#ifdef CONFIG_LS2080A
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enum srds_prtcl {
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NONE = 0,
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PCIE1,
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PCIE2,
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PCIE3,
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PCIE4,
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SATA1,
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SATA2,
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XAUI1,
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XAUI2,
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XFI1,
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XFI2,
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XFI3,
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XFI4,
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XFI5,
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XFI6,
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XFI7,
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XFI8,
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SGMII1,
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SGMII2,
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SGMII3,
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SGMII4,
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SGMII5,
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SGMII6,
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SGMII7,
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SGMII8,
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SGMII9,
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SGMII10,
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SGMII11,
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SGMII12,
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SGMII13,
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SGMII14,
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SGMII15,
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SGMII16,
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QSGMII_A, /* A indicates MACs 1-4 */
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QSGMII_B, /* B indicates MACs 5-8 */
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QSGMII_C, /* C indicates MACs 9-12 */
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QSGMII_D, /* D indicates MACs 12-16 */
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SERDES_PRCTL_COUNT
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};
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enum srds {
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FSL_SRDS_1 = 0,
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FSL_SRDS_2 = 1,
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};
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#elif defined(CONFIG_FSL_LSCH2)
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enum srds_prtcl {
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NONE = 0,
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PCIE1,
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PCIE2,
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PCIE3,
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PCIE4,
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SATA1,
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SATA2,
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SRIO1,
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SRIO2,
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SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3,
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SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5,
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SGMII_FM1_DTSEC6,
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SGMII_FM1_DTSEC9,
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SGMII_FM1_DTSEC10,
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SGMII_FM2_DTSEC1,
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SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3,
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SGMII_FM2_DTSEC4,
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SGMII_FM2_DTSEC5,
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SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC9,
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SGMII_FM2_DTSEC10,
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SGMII_TSEC1,
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SGMII_TSEC2,
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SGMII_TSEC3,
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SGMII_TSEC4,
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XAUI_FM1,
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XAUI_FM2,
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AURORA,
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CPRI1,
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CPRI2,
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CPRI3,
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CPRI4,
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CPRI5,
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CPRI6,
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CPRI7,
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CPRI8,
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XAUI_FM1_MAC9,
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XAUI_FM1_MAC10,
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XAUI_FM2_MAC9,
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XAUI_FM2_MAC10,
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HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC10,
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HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC10,
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QSGMII_FM1_A, /* A indicates MACs 1,2,5,6 */
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QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
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QSGMII_FM2_A,
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QSGMII_FM2_B,
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XFI_FM1_MAC1,
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XFI_FM1_MAC2,
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XFI_FM1_MAC9,
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XFI_FM1_MAC10,
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XFI_FM2_MAC9,
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XFI_FM2_MAC10,
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INTERLAKEN,
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QSGMII_SW1_A, /* Indicates ports on L2 Switch */
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QSGMII_SW1_B,
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SGMII_2500_FM1_DTSEC1,
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SGMII_2500_FM1_DTSEC2,
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SGMII_2500_FM1_DTSEC3,
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SGMII_2500_FM1_DTSEC4,
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SGMII_2500_FM1_DTSEC5,
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SGMII_2500_FM1_DTSEC6,
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SGMII_2500_FM1_DTSEC9,
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SGMII_2500_FM1_DTSEC10,
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SGMII_2500_FM2_DTSEC1,
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SGMII_2500_FM2_DTSEC2,
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SGMII_2500_FM2_DTSEC3,
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SGMII_2500_FM2_DTSEC4,
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SGMII_2500_FM2_DTSEC5,
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SGMII_2500_FM2_DTSEC6,
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SGMII_2500_FM2_DTSEC9,
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SGMII_2500_FM2_DTSEC10,
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TX_CLK,
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SERDES_PRCTL_COUNT
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};
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enum srds {
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FSL_SRDS_1 = 0,
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FSL_SRDS_2 = 1,
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};
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#endif
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int is_serdes_configured(enum srds_prtcl device);
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void fsl_serdes_init(void);
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int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
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int is_serdes_prtcl_valid(int serdes, u32 prtcl);
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#ifdef CONFIG_FSL_LSCH2
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const char *serdes_clock_to_string(u32 clock);
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int get_serdes_protocol(void);
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#endif
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#endif /* __FSL_SERDES_H__ */
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