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326e05c5e2
Add trivial reset driver extension to the CPG clock driver. The change turns current CPG UCLASS_CLK driver instance into an UCLASS_NOP proxy driver, which in turn binds both generic rcar3_clk UCLASS_CLK clock driver as well as generic rcar_rst UCLASS_RESET reset driver to the CPG DT node. This way, any other drivers which use the 'reset' DT property can now obtain valid reset handle backed by a reset driver. The clock tables have been updated to represent the CPG driver and only implement the generic CPG proxy driver bind call, which binds the clock and reset drivers. The DM_RESET is now enabled for all R-Car Gen3 platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
133 lines
3.9 KiB
C
133 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* R-Car Gen3 Clock Pulse Generator
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*
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* Copyright (C) 2015-2018 Glider bvba
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* Copyright (C) 2018 Renesas Electronics Corp.
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*
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*/
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#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
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#define __CLK_RENESAS_RCAR_GEN3_CPG_H__
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enum rcar_gen3_clk_types {
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CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
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CLK_TYPE_GEN3_PLL0,
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CLK_TYPE_GEN3_PLL1,
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CLK_TYPE_GEN3_PLL2,
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CLK_TYPE_GEN3_PLL3,
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CLK_TYPE_GEN3_PLL4,
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CLK_TYPE_GEN3_SDH,
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CLK_TYPE_GEN3_SD,
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CLK_TYPE_GEN3_R,
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CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
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CLK_TYPE_GEN3_Z,
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CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
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CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
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CLK_TYPE_GEN3_RPCSRC,
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CLK_TYPE_GEN3_D3_RPCSRC,
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CLK_TYPE_GEN3_E3_RPCSRC,
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CLK_TYPE_GEN3_RPC,
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CLK_TYPE_GEN3_RPCD2,
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CLK_TYPE_GEN4_MAIN,
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CLK_TYPE_GEN4_PLL1,
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CLK_TYPE_GEN4_PLL2X_3X, /* PLL[23][01] */
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CLK_TYPE_GEN4_PLL5,
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CLK_TYPE_GEN4_SDH,
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CLK_TYPE_GEN4_SD,
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CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */
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CLK_TYPE_GEN4_Z,
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CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */
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CLK_TYPE_GEN4_RPCSRC,
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CLK_TYPE_GEN4_RPC,
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CLK_TYPE_GEN4_RPCD2,
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/* SoC specific definitions start here */
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CLK_TYPE_GEN3_SOC_BASE,
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};
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#define DEF_GEN3_SDH(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
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#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
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#define DEF_GEN3_RPCD2(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPCD2, _parent, .offset = _offset)
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#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
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(_parent0) << 16 | (_parent1), \
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.div = (_div0) << 16 | (_div1), .offset = _md)
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#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
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_div_clean) \
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DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
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_parent_clean, _div_clean)
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#define DEF_GEN3_OSC(_name, _id, _parent, _div) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
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#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
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(_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
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#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \
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DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
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#define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_D3_RPCSRC, \
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(_parent0) << 16 | (_parent1), .div = 5)
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#define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \
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(_parent0) << 16 | (_parent1), .div = 8)
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#define DEF_GEN4_SDH(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
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#define DEF_GEN4_SD(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
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#define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \
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(_parent0) << 16 | (_parent1), \
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.div = (_div0) << 16 | (_div1), .offset = _md)
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#define DEF_GEN4_OSC(_name, _id, _parent, _div) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
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#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \
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DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
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struct rcar_gen3_cpg_pll_config {
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u8 extal_div;
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u8 pll1_mult;
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u8 pll1_div;
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u8 pll3_mult;
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u8 pll3_div;
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u8 osc_prediv;
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u8 pll5_mult;
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u8 pll5_div;
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};
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#define CPG_RST_MODEMR 0x060
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#define CPG_RPCCKCR 0x238
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#define CPG_RCKCR 0x240
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struct gen3_clk_priv {
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void __iomem *base;
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struct cpg_mssr_info *info;
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struct clk clk_extal;
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struct clk clk_extalr;
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bool sscg;
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const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
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};
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int gen3_cpg_bind(struct udevice *parent);
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extern const struct clk_ops gen3_clk_ops;
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#endif
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