mirror of
https://github.com/AsahiLinux/u-boot
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c05be59ca8
Split master clock in 2 controlling block: one for prescaler one for
divider. This will allow referencing correctly the CPU clock and
master clock in device trees.
Reported-by: Eugen Hristev <eugen.hristev@microchip.com>
Fixes: a64862284f
("clk: at91: sam9x60: add support compatible with
CCF")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
1409 lines
37 KiB
C
1409 lines
37 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* SAMA7G5 PMC clock support.
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*
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* Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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*
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* Based on drivers/clk/at91/sama7g5.c from Linux.
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dt-bindings/clk/at91.h>
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#include <linux/clk-provider.h>
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#include "pmc.h"
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/**
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* Clock identifiers to be used in conjunction with macros like
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* AT91_TO_CLK_ID()
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*
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* @ID_MD_SLCK: TD slow clock identifier
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* @ID_TD_SLCK: MD slow clock identifier
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* @ID_MAIN_XTAL: Main Xtal clock identifier
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* @ID_MAIN_RC: Main RC clock identifier
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* @ID_MAIN_RC_OSC: Main RC Oscillator clock identifier
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* @ID_MAIN_OSC: Main Oscillator clock identifier
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* @ID_MAINCK: MAINCK clock identifier
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* @ID_PLL_CPU_FRAC: CPU PLL fractional clock identifier
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* @ID_PLL_CPU_DIV: CPU PLL divider clock identifier
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* @ID_PLL_SYS_FRAC: SYS PLL fractional clock identifier
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* @ID_PLL_SYS_DIV: SYS PLL divider clock identifier
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* @ID_PLL_DDR_FRAC: DDR PLL fractional clock identifier
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* @ID_PLL_DDR_DIV: DDR PLL divider clock identifier
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* @ID_PLL_IMG_FRAC: IMC PLL fractional clock identifier
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* @ID_PLL_IMG_DIV: IMG PLL divider clock identifier
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* @ID_PLL_BAUD_FRAC: Baud PLL fractional clock identifier
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* @ID_PLL_BAUD_DIV: Baud PLL divider clock identifier
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* @ID_PLL_AUDIO_FRAC: Audio PLL fractional clock identifier
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* @ID_PLL_AUDIO_DIVPMC: Audio PLL PMC divider clock identifier
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* @ID_PLL_AUDIO_DIVIO: Audio PLL IO divider clock identifier
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* @ID_PLL_ETH_FRAC: Ethernet PLL fractional clock identifier
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* @ID_PLL_ETH_DIV: Ethernet PLL divider clock identifier
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* @ID_MCK0_PRES: MCK0 PRES clock identifier
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* @ID_MCK0_DIV: MCK0 DIV clock identifier
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* @ID_MCK1: MCK1 clock identifier
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* @ID_MCK2: MCK2 clock identifier
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* @ID_MCK3: MCK3 clock identifier
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* @ID_MCK4: MCK4 clock identifier
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* @ID_UTMI: UTMI clock identifier
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* @ID_PROG0: Programmable 0 clock identifier
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* @ID_PROG1: Programmable 1 clock identifier
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* @ID_PROG2: Programmable 2 clock identifier
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* @ID_PROG3: Programmable 3 clock identifier
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* @ID_PROG4: Programmable 4 clock identifier
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* @ID_PROG5: Programmable 5 clock identifier
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* @ID_PROG6: Programmable 6 clock identifier
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* @ID_PROG7: Programmable 7 clock identifier
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* @ID_PCK0: System clock 0 clock identifier
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* @ID_PCK1: System clock 1 clock identifier
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* @ID_PCK2: System clock 2 clock identifier
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* @ID_PCK3: System clock 3 clock identifier
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* @ID_PCK4: System clock 4 clock identifier
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* @ID_PCK5: System clock 5 clock identifier
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* @ID_PCK6: System clock 6 clock identifier
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* @ID_PCK7: System clock 7 clock identifier
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*/
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enum pmc_clk_ids {
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ID_MD_SLCK = 0,
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ID_TD_SLCK = 1,
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ID_MAIN_XTAL = 2,
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ID_MAIN_RC = 3,
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ID_MAIN_RC_OSC = 4,
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ID_MAIN_OSC = 5,
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ID_MAINCK = 6,
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ID_PLL_CPU_FRAC = 7,
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ID_PLL_CPU_DIV = 8,
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ID_PLL_SYS_FRAC = 9,
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ID_PLL_SYS_DIV = 10,
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ID_PLL_DDR_FRAC = 11,
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ID_PLL_DDR_DIV = 12,
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ID_PLL_IMG_FRAC = 13,
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ID_PLL_IMG_DIV = 14,
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ID_PLL_BAUD_FRAC = 15,
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ID_PLL_BAUD_DIV = 16,
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ID_PLL_AUDIO_FRAC = 17,
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ID_PLL_AUDIO_DIVPMC = 18,
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ID_PLL_AUDIO_DIVIO = 19,
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ID_PLL_ETH_FRAC = 20,
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ID_PLL_ETH_DIV = 21,
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ID_MCK0_DIV = 22,
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ID_MCK1 = 23,
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ID_MCK2 = 24,
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ID_MCK3 = 25,
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ID_MCK4 = 26,
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ID_UTMI = 27,
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ID_PROG0 = 28,
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ID_PROG1 = 29,
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ID_PROG2 = 30,
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ID_PROG3 = 31,
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ID_PROG4 = 32,
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ID_PROG5 = 33,
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ID_PROG6 = 34,
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ID_PROG7 = 35,
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ID_PCK0 = 36,
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ID_PCK1 = 37,
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ID_PCK2 = 38,
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ID_PCK3 = 39,
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ID_PCK4 = 40,
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ID_PCK5 = 41,
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ID_PCK6 = 42,
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ID_PCK7 = 43,
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ID_MCK0_PRES = 44,
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ID_MAX,
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};
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/**
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* PLL type identifiers
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* @PLL_TYPE_FRAC: fractional PLL identifier
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* @PLL_TYPE_DIV: divider PLL identifier
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*/
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enum pll_type {
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PLL_TYPE_FRAC,
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PLL_TYPE_DIV,
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};
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/* Clock names used as parents for multiple clocks. */
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static const char *clk_names[] = {
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[ID_MAIN_RC_OSC] = "main_rc_osc",
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[ID_MAIN_OSC] = "main_osc",
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[ID_MAINCK] = "mainck",
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[ID_PLL_CPU_DIV] = "cpupll_divpmcck",
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[ID_PLL_SYS_DIV] = "syspll_divpmcck",
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[ID_PLL_DDR_DIV] = "ddrpll_divpmcck",
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[ID_PLL_IMG_DIV] = "imgpll_divpmcck",
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[ID_PLL_BAUD_DIV] = "baudpll_divpmcck",
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[ID_PLL_AUDIO_DIVPMC] = "audiopll_divpmcck",
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[ID_PLL_AUDIO_DIVIO] = "audiopll_diviock",
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[ID_PLL_ETH_DIV] = "ethpll_divpmcck",
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[ID_MCK0_DIV] = "mck0_div",
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[ID_MCK0_PRES] = "mck0_pres",
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};
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/* Fractional PLL output range. */
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static const struct clk_range pll_outputs[] = {
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{ .min = 2343750, .max = 1200000000 },
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};
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/* PLL characteristics. */
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static const struct clk_pll_characteristics pll_characteristics = {
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.input = { .min = 12000000, .max = 50000000 },
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.num_output = ARRAY_SIZE(pll_outputs),
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.output = pll_outputs,
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};
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/* Layout for fractional PLLs. */
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static const struct clk_pll_layout pll_layout_frac = {
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.mul_mask = GENMASK(31, 24),
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.frac_mask = GENMASK(21, 0),
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.mul_shift = 24,
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.frac_shift = 0,
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};
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/* Layout for DIVPMC dividers. */
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static const struct clk_pll_layout pll_layout_divpmc = {
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.div_mask = GENMASK(7, 0),
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.endiv_mask = BIT(29),
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.div_shift = 0,
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.endiv_shift = 29,
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};
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/* Layout for DIVIO dividers. */
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static const struct clk_pll_layout pll_layout_divio = {
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.div_mask = GENMASK(19, 12),
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.endiv_mask = BIT(30),
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.div_shift = 12,
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.endiv_shift = 30,
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};
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/* MCK0 characteristics. */
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static const struct clk_master_characteristics mck0_characteristics = {
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.output = { .min = 140000000, .max = 200000000 },
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.divisors = { 1, 2, 4, 3, 5 },
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.have_div3_pres = 1,
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};
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/* MCK0 layout. */
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static const struct clk_master_layout mck0_layout = {
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.mask = 0x773,
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.pres_shift = 4,
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.offset = 0x28,
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};
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/* Programmable clock layout. */
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static const struct clk_programmable_layout programmable_layout = {
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.pres_mask = 0xff,
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.pres_shift = 8,
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.css_mask = 0x1f,
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.have_slck_mck = 0,
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.is_pres_direct = 1,
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};
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/* Peripheral clock layout. */
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static const struct clk_pcr_layout sama7g5_pcr_layout = {
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.offset = 0x88,
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.cmd = BIT(31),
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.gckcss_mask = GENMASK(12, 8),
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.pid_mask = GENMASK(6, 0),
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.div_mask = GENMASK(15, 14),
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};
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/**
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* PLL clocks description
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* @n: clock name
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* @p: clock parent
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* @l: clock layout
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* @t: clock type
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* @c: true if clock is critical and cannot be disabled
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* @id: clock id corresponding to PLL driver
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* @cid: clock id corresponding to clock subsystem
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*/
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static const struct {
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const char *n;
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const char *p;
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const struct clk_pll_layout *l;
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u8 t;
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u8 c;
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u8 id;
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u8 cid;
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} sama7g5_plls[] = {
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{
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.n = "cpupll_fracck",
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.p = "mainck",
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.l = &pll_layout_frac,
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.t = PLL_TYPE_FRAC,
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.c = 1,
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.id = 0,
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.cid = ID_PLL_CPU_FRAC,
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},
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{
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.n = "cpupll_divpmcck",
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.p = "cpupll_fracck",
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.l = &pll_layout_divpmc,
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.t = PLL_TYPE_DIV,
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.c = 1,
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.id = 0,
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.cid = ID_PLL_CPU_DIV,
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},
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{
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.n = "syspll_fracck",
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.p = "mainck",
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.l = &pll_layout_frac,
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.t = PLL_TYPE_FRAC,
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.c = 1,
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.id = 1,
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.cid = ID_PLL_SYS_FRAC,
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},
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{
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.n = "syspll_divpmcck",
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.p = "syspll_fracck",
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.l = &pll_layout_divpmc,
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.t = PLL_TYPE_DIV,
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.c = 1,
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.id = 1,
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.cid = ID_PLL_SYS_DIV,
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},
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{
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.n = "ddrpll_fracck",
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.p = "mainck",
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.l = &pll_layout_frac,
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.t = PLL_TYPE_FRAC,
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.c = 1,
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.id = 2,
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.cid = ID_PLL_DDR_FRAC,
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},
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{
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.n = "ddrpll_divpmcck",
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.p = "ddrpll_fracck",
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.l = &pll_layout_divpmc,
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.t = PLL_TYPE_DIV,
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.c = 1,
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.id = 2,
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.cid = ID_PLL_DDR_DIV,
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},
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{
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.n = "imgpll_fracck",
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.p = "mainck",
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.l = &pll_layout_frac,
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.t = PLL_TYPE_FRAC,
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.id = 3,
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.cid = ID_PLL_IMG_FRAC,
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},
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{
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.n = "imgpll_divpmcck",
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.p = "imgpll_fracck",
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.l = &pll_layout_divpmc,
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.t = PLL_TYPE_DIV,
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.id = 3,
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.cid = ID_PLL_IMG_DIV
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},
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{
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.n = "baudpll_fracck",
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.p = "mainck",
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.l = &pll_layout_frac,
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.t = PLL_TYPE_FRAC,
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.id = 4,
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.cid = ID_PLL_BAUD_FRAC,
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},
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{
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.n = "baudpll_divpmcck",
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.p = "baudpll_fracck",
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.l = &pll_layout_divpmc,
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.t = PLL_TYPE_DIV,
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.id = 4,
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.cid = ID_PLL_BAUD_DIV,
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},
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{
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.n = "audiopll_fracck",
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.p = "main_osc",
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.l = &pll_layout_frac,
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.t = PLL_TYPE_FRAC,
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.id = 5,
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.cid = ID_PLL_AUDIO_FRAC,
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},
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{
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.n = "audiopll_divpmcck",
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.p = "audiopll_fracck",
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.l = &pll_layout_divpmc,
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.t = PLL_TYPE_DIV,
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.id = 5,
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.cid = ID_PLL_AUDIO_DIVPMC,
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},
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{
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.n = "audiopll_diviock",
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.p = "audiopll_fracck",
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.l = &pll_layout_divio,
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.t = PLL_TYPE_DIV,
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.id = 5,
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.cid = ID_PLL_AUDIO_DIVIO,
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},
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{
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.n = "ethpll_fracck",
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.p = "main_osc",
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.l = &pll_layout_frac,
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.t = PLL_TYPE_FRAC,
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.id = 6,
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.cid = ID_PLL_ETH_FRAC,
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},
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{
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.n = "ethpll_divpmcck",
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.p = "ethpll_fracck",
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.l = &pll_layout_divpmc,
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.t = PLL_TYPE_DIV,
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.id = 6,
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.cid = ID_PLL_ETH_DIV,
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},
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};
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/**
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* Master clock (MCK[1..4]) description
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* @n: clock name
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* @ep: extra parents names array
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* @ep_chg_chg_id: index in parents array that specifies the changeable
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* parent
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* @ep_count: extra parents count
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* @ep_mux_table: mux table for extra parents
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* @ep_clk_mux_table: mux table to deal with subsystem clock ids
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* @id: clock id corresponding to MCK driver
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* @cid: clock id corresponding to clock subsystem
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* @c: true if clock is critical and cannot be disabled
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*/
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static const struct {
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const char *n;
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const char *ep[4];
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u8 ep_count;
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u8 ep_mux_table[4];
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u8 ep_clk_mux_table[4];
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u8 id;
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u8 cid;
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u8 c;
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} sama7g5_mckx[] = {
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{
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.n = "mck1",
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.id = 1,
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.cid = ID_MCK1,
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.ep = { "syspll_divpmcck", },
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.ep_mux_table = { 5, },
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.ep_clk_mux_table = { ID_PLL_SYS_DIV, },
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.ep_count = 1,
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.c = 1,
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},
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{
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.n = "mck2",
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.id = 2,
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.cid = ID_MCK2,
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.ep = { "ddrpll_divpmcck", },
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.ep_mux_table = { 6, },
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.ep_clk_mux_table = { ID_PLL_DDR_DIV, },
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.ep_count = 1,
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.c = 1,
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},
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{
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.n = "mck3",
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.id = 3,
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.cid = ID_MCK3,
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.ep = { "syspll_divpmcck", "ddrpll_divpmcck", "imgpll_divpmcck", },
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.ep_mux_table = { 5, 6, 7, },
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.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_DDR_DIV, ID_PLL_IMG_DIV, },
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.ep_count = 3,
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},
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{
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.n = "mck4",
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.id = 4,
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.cid = ID_MCK4,
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.ep = { "syspll_divpmcck", },
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.ep_mux_table = { 5, },
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.ep_clk_mux_table = { ID_PLL_SYS_DIV, },
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.ep_count = 1,
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.c = 1,
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},
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};
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/**
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* Programmable clock description
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* @n: clock name
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* @cid: clock id corresponding to clock subsystem
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*/
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static const struct {
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const char *n;
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u8 cid;
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} sama7g5_prog[] = {
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{ .n = "prog0", .cid = ID_PROG0, },
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{ .n = "prog1", .cid = ID_PROG1, },
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{ .n = "prog2", .cid = ID_PROG2, },
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{ .n = "prog3", .cid = ID_PROG3, },
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{ .n = "prog4", .cid = ID_PROG4, },
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{ .n = "prog5", .cid = ID_PROG5, },
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{ .n = "prog6", .cid = ID_PROG6, },
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{ .n = "prog7", .cid = ID_PROG7, },
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};
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/* Mux table for programmable clocks. */
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static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, };
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/**
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* System clock description
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* @n: clock name
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* @p: parent clock name
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* @id: clock id corresponding to system clock driver
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* @cid: clock id corresponding to clock subsystem
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*/
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static const struct {
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const char *n;
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const char *p;
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u8 id;
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u8 cid;
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} sama7g5_systemck[] = {
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{ .n = "pck0", .p = "prog0", .id = 8, .cid = ID_PCK0, },
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{ .n = "pck1", .p = "prog1", .id = 9, .cid = ID_PCK1, },
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|
{ .n = "pck2", .p = "prog2", .id = 10, .cid = ID_PCK2, },
|
|
{ .n = "pck3", .p = "prog3", .id = 11, .cid = ID_PCK3, },
|
|
{ .n = "pck4", .p = "prog4", .id = 12, .cid = ID_PCK4, },
|
|
{ .n = "pck5", .p = "prog5", .id = 13, .cid = ID_PCK5, },
|
|
{ .n = "pck6", .p = "prog6", .id = 14, .cid = ID_PCK6, },
|
|
{ .n = "pck7", .p = "prog7", .id = 15, .cid = ID_PCK7, },
|
|
};
|
|
|
|
/**
|
|
* Peripheral clock description
|
|
* @n: clock name
|
|
* @p: clock parent name
|
|
* @r: clock range values
|
|
* @id: clock id
|
|
*/
|
|
static const struct {
|
|
const char *n;
|
|
const char *p;
|
|
struct clk_range r;
|
|
u8 id;
|
|
} sama7g5_periphck[] = {
|
|
{ .n = "pioA_clk", .p = "mck0_div", .id = 11, },
|
|
{ .n = "sfr_clk", .p = "mck1", .id = 19, },
|
|
{ .n = "hsmc_clk", .p = "mck1", .id = 21, },
|
|
{ .n = "xdmac0_clk", .p = "mck1", .id = 22, },
|
|
{ .n = "xdmac1_clk", .p = "mck1", .id = 23, },
|
|
{ .n = "xdmac2_clk", .p = "mck1", .id = 24, },
|
|
{ .n = "acc_clk", .p = "mck1", .id = 25, },
|
|
{ .n = "aes_clk", .p = "mck1", .id = 27, },
|
|
{ .n = "tzaesbasc_clk", .p = "mck1", .id = 28, },
|
|
{ .n = "asrc_clk", .p = "mck1", .id = 30, .r = { .max = 200000000, }, },
|
|
{ .n = "cpkcc_clk", .p = "mck0_div", .id = 32, },
|
|
{ .n = "csi_clk", .p = "mck3", .id = 33, .r = { .max = 266000000, }, },
|
|
{ .n = "csi2dc_clk", .p = "mck3", .id = 34, .r = { .max = 266000000, }, },
|
|
{ .n = "eic_clk", .p = "mck1", .id = 37, },
|
|
{ .n = "flex0_clk", .p = "mck1", .id = 38, },
|
|
{ .n = "flex1_clk", .p = "mck1", .id = 39, },
|
|
{ .n = "flex2_clk", .p = "mck1", .id = 40, },
|
|
{ .n = "flex3_clk", .p = "mck1", .id = 41, },
|
|
{ .n = "flex4_clk", .p = "mck1", .id = 42, },
|
|
{ .n = "flex5_clk", .p = "mck1", .id = 43, },
|
|
{ .n = "flex6_clk", .p = "mck1", .id = 44, },
|
|
{ .n = "flex7_clk", .p = "mck1", .id = 45, },
|
|
{ .n = "flex8_clk", .p = "mck1", .id = 46, },
|
|
{ .n = "flex9_clk", .p = "mck1", .id = 47, },
|
|
{ .n = "flex10_clk", .p = "mck1", .id = 48, },
|
|
{ .n = "flex11_clk", .p = "mck1", .id = 49, },
|
|
{ .n = "gmac0_clk", .p = "mck1", .id = 51, },
|
|
{ .n = "gmac1_clk", .p = "mck1", .id = 52, },
|
|
{ .n = "gmac0_tsu_clk", .p = "mck1", .id = 53, },
|
|
{ .n = "gmac1_tsu_clk", .p = "mck1", .id = 54, },
|
|
{ .n = "icm_clk", .p = "mck1", .id = 55, },
|
|
{ .n = "isc_clk", .p = "mck3", .id = 56, .r = { .max = 266000000, }, },
|
|
{ .n = "i2smcc0_clk", .p = "mck1", .id = 57, .r = { .max = 200000000, }, },
|
|
{ .n = "i2smcc1_clk", .p = "mck1", .id = 58, .r = { .max = 200000000, }, },
|
|
{ .n = "matrix_clk", .p = "mck1", .id = 60, },
|
|
{ .n = "mcan0_clk", .p = "mck1", .id = 61, .r = { .max = 200000000, }, },
|
|
{ .n = "mcan1_clk", .p = "mck1", .id = 62, .r = { .max = 200000000, }, },
|
|
{ .n = "mcan2_clk", .p = "mck1", .id = 63, .r = { .max = 200000000, }, },
|
|
{ .n = "mcan3_clk", .p = "mck1", .id = 64, .r = { .max = 200000000, }, },
|
|
{ .n = "mcan4_clk", .p = "mck1", .id = 65, .r = { .max = 200000000, }, },
|
|
{ .n = "mcan5_clk", .p = "mck1", .id = 66, .r = { .max = 200000000, }, },
|
|
{ .n = "pdmc0_clk", .p = "mck1", .id = 68, .r = { .max = 200000000, }, },
|
|
{ .n = "pdmc1_clk", .p = "mck1", .id = 69, .r = { .max = 200000000, }, },
|
|
{ .n = "pit64b0_clk", .p = "mck1", .id = 70, },
|
|
{ .n = "pit64b1_clk", .p = "mck1", .id = 71, },
|
|
{ .n = "pit64b2_clk", .p = "mck1", .id = 72, },
|
|
{ .n = "pit64b3_clk", .p = "mck1", .id = 73, },
|
|
{ .n = "pit64b4_clk", .p = "mck1", .id = 74, },
|
|
{ .n = "pit64b5_clk", .p = "mck1", .id = 75, },
|
|
{ .n = "pwm_clk", .p = "mck1", .id = 77, },
|
|
{ .n = "qspi0_clk", .p = "mck1", .id = 78, },
|
|
{ .n = "qspi1_clk", .p = "mck1", .id = 79, },
|
|
{ .n = "sdmmc0_clk", .p = "mck1", .id = 80, },
|
|
{ .n = "sdmmc1_clk", .p = "mck1", .id = 81, },
|
|
{ .n = "sdmmc2_clk", .p = "mck1", .id = 82, },
|
|
{ .n = "sha_clk", .p = "mck1", .id = 83, },
|
|
{ .n = "spdifrx_clk", .p = "mck1", .id = 84, .r = { .max = 200000000, }, },
|
|
{ .n = "spdiftx_clk", .p = "mck1", .id = 85, .r = { .max = 200000000, }, },
|
|
{ .n = "ssc0_clk", .p = "mck1", .id = 86, .r = { .max = 200000000, }, },
|
|
{ .n = "ssc1_clk", .p = "mck1", .id = 87, .r = { .max = 200000000, }, },
|
|
{ .n = "tcb0_ch0_clk", .p = "mck1", .id = 88, .r = { .max = 200000000, }, },
|
|
{ .n = "tcb0_ch1_clk", .p = "mck1", .id = 89, .r = { .max = 200000000, }, },
|
|
{ .n = "tcb0_ch2_clk", .p = "mck1", .id = 90, .r = { .max = 200000000, }, },
|
|
{ .n = "tcb1_ch0_clk", .p = "mck1", .id = 91, .r = { .max = 200000000, }, },
|
|
{ .n = "tcb1_ch1_clk", .p = "mck1", .id = 92, .r = { .max = 200000000, }, },
|
|
{ .n = "tcb1_ch2_clk", .p = "mck1", .id = 93, .r = { .max = 200000000, }, },
|
|
{ .n = "tcpca_clk", .p = "mck1", .id = 94, },
|
|
{ .n = "tcpcb_clk", .p = "mck1", .id = 95, },
|
|
{ .n = "tdes_clk", .p = "mck1", .id = 96, },
|
|
{ .n = "trng_clk", .p = "mck1", .id = 97, },
|
|
{ .n = "udphsa_clk", .p = "mck1", .id = 104, },
|
|
{ .n = "udphsb_clk", .p = "mck1", .id = 105, },
|
|
{ .n = "uhphs_clk", .p = "mck1", .id = 106, },
|
|
};
|
|
|
|
/**
|
|
* Generic clock description
|
|
* @n: clock name
|
|
* @ep: extra parents names
|
|
* @ep_mux_table: extra parents mux table
|
|
* @ep_clk_mux_table: extra parents clock mux table (for CCF)
|
|
* @r: clock output range
|
|
* @ep_count: extra parents count
|
|
* @id: clock id
|
|
*/
|
|
static const struct {
|
|
const char *n;
|
|
const char *ep[8];
|
|
const char ep_mux_table[8];
|
|
const char ep_clk_mux_table[8];
|
|
struct clk_range r;
|
|
u8 ep_count;
|
|
u8 id;
|
|
} sama7g5_gck[] = {
|
|
{
|
|
.n = "adc_gclk",
|
|
.id = 26,
|
|
.r = { .max = 100000000, },
|
|
.ep = { "syspll_divpmcck", "imgpll_divpmcck", "audiopll_divpmcck", },
|
|
.ep_mux_table = { 5, 7, 9, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_IMG_DIV,
|
|
ID_PLL_AUDIO_DIVPMC, },
|
|
.ep_count = 3,
|
|
},
|
|
|
|
{
|
|
.n = "asrc_gclk",
|
|
.id = 30,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "audiopll_divpmcck", },
|
|
.ep_mux_table = { 9, },
|
|
.ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, },
|
|
.ep_count = 1,
|
|
},
|
|
|
|
{
|
|
.n = "csi_gclk",
|
|
.id = 33,
|
|
.r = { .max = 27000000 },
|
|
.ep = { "ddrpll_divpmcck", "imgpll_divpmcck", },
|
|
.ep_clk_mux_table = { ID_PLL_DDR_DIV, ID_PLL_IMG_DIV, },
|
|
.ep_mux_table = { 6, 7, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "flex0_gclk",
|
|
.id = 38,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "flex1_gclk",
|
|
.id = 39,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "flex2_gclk",
|
|
.id = 40,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "flex3_gclk",
|
|
.id = 41,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "flex4_gclk",
|
|
.id = 42,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "flex5_gclk",
|
|
.id = 43,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "flex6_gclk",
|
|
.id = 44,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "flex7_gclk",
|
|
.id = 45,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "flex8_gclk",
|
|
.id = 46,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "flex9_gclk",
|
|
.id = 47,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "flex10_gclk",
|
|
.id = 48,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "flex11_gclk",
|
|
.id = 49,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "gmac0_gclk",
|
|
.id = 51,
|
|
.r = { .max = 125000000 },
|
|
.ep = { "ethpll_divpmcck", },
|
|
.ep_clk_mux_table = { ID_PLL_ETH_DIV, },
|
|
.ep_mux_table = { 10, },
|
|
.ep_count = 1,
|
|
},
|
|
|
|
{
|
|
.n = "gmac1_gclk",
|
|
.id = 52,
|
|
.r = { .max = 50000000 },
|
|
.ep = { "ethpll_divpmcck", },
|
|
.ep_mux_table = { 10, },
|
|
.ep_clk_mux_table = { ID_PLL_ETH_DIV, },
|
|
.ep_count = 1,
|
|
},
|
|
|
|
{
|
|
.n = "gmac0_tsu_gclk",
|
|
.id = 53,
|
|
.r = { .max = 300000000 },
|
|
.ep = { "audiopll_divpmcck", "ethpll_divpmcck", },
|
|
.ep_mux_table = { 9, 10, },
|
|
.ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, ID_PLL_ETH_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "gmac1_tsu_gclk",
|
|
.id = 54,
|
|
.r = { .max = 300000000 },
|
|
.ep = { "audiopll_divpmcck", "ethpll_divpmcck", },
|
|
.ep_mux_table = { 9, 10, },
|
|
.ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, ID_PLL_ETH_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "i2smcc0_gclk",
|
|
.id = 57,
|
|
.r = { .max = 100000000 },
|
|
.ep = { "syspll_divpmcck", "audiopll_divpmcck", },
|
|
.ep_mux_table = { 5, 9, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_AUDIO_DIVPMC, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "i2smcc1_gclk",
|
|
.id = 58,
|
|
.r = { .max = 100000000 },
|
|
.ep = { "syspll_divpmcck", "audiopll_divpmcck", },
|
|
.ep_mux_table = { 5, 9, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_AUDIO_DIVPMC, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "mcan0_gclk",
|
|
.id = 61,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "mcan1_gclk",
|
|
.id = 62,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "mcan2_gclk",
|
|
.id = 63,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "mcan3_gclk",
|
|
.id = 64,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "mcan4_gclk",
|
|
.id = 65,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "mcan5_gclk",
|
|
.id = 66,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "pdmc0_gclk",
|
|
.id = 68,
|
|
.r = { .max = 50000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "pdmc1_gclk",
|
|
.id = 69,
|
|
.r = { .max = 50000000, },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "pit64b0_gclk",
|
|
.id = 70,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
|
|
"audiopll_divpmcck", "ethpll_divpmcck", },
|
|
.ep_mux_table = { 5, 7, 8, 9, 10, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_IMG_DIV,
|
|
ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC,
|
|
ID_PLL_ETH_DIV, },
|
|
.ep_count = 5,
|
|
},
|
|
|
|
{
|
|
.n = "pit64b1_gclk",
|
|
.id = 71,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
|
|
"audiopll_divpmcck", "ethpll_divpmcck", },
|
|
.ep_mux_table = { 5, 7, 8, 9, 10, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_IMG_DIV,
|
|
ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC,
|
|
ID_PLL_ETH_DIV, },
|
|
.ep_count = 5,
|
|
},
|
|
|
|
{
|
|
.n = "pit64b2_gclk",
|
|
.id = 72,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
|
|
"audiopll_divpmcck", "ethpll_divpmcck", },
|
|
.ep_mux_table = { 5, 7, 8, 9, 10, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_IMG_DIV,
|
|
ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC,
|
|
ID_PLL_ETH_DIV, },
|
|
.ep_count = 5,
|
|
},
|
|
|
|
{
|
|
.n = "pit64b3_gclk",
|
|
.id = 73,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
|
|
"audiopll_divpmcck", "ethpll_divpmcck", },
|
|
.ep_mux_table = { 5, 7, 8, 9, 10, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_IMG_DIV,
|
|
ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC,
|
|
ID_PLL_ETH_DIV, },
|
|
.ep_count = 5,
|
|
},
|
|
|
|
{
|
|
.n = "pit64b4_gclk",
|
|
.id = 74,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
|
|
"audiopll_divpmcck", "ethpll_divpmcck", },
|
|
.ep_mux_table = { 5, 7, 8, 9, 10, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_IMG_DIV,
|
|
ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC,
|
|
ID_PLL_ETH_DIV, },
|
|
.ep_count = 5,
|
|
},
|
|
|
|
{
|
|
.n = "pit64b5_gclk",
|
|
.id = 75,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
|
|
"audiopll_divpmcck", "ethpll_divpmcck", },
|
|
.ep_mux_table = { 5, 7, 8, 9, 10, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_IMG_DIV,
|
|
ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC,
|
|
ID_PLL_ETH_DIV, },
|
|
.ep_count = 5,
|
|
},
|
|
|
|
{
|
|
.n = "qspi0_gclk",
|
|
.id = 78,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_IMG_DIV,
|
|
ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC,
|
|
ID_PLL_ETH_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "qspi1_gclk",
|
|
.id = 79,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "sdmmc0_gclk",
|
|
.id = 80,
|
|
.r = { .max = 208000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "sdmmc1_gclk",
|
|
.id = 81,
|
|
.r = { .max = 208000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "sdmmc2_gclk",
|
|
.id = 82,
|
|
.r = { .max = 208000000 },
|
|
.ep = { "syspll_divpmcck", "baudpll_divpmcck", },
|
|
.ep_mux_table = { 5, 8, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "spdifrx_gclk",
|
|
.id = 84,
|
|
.r = { .max = 150000000 },
|
|
.ep = { "syspll_divpmcck", "audiopll_divpmcck", },
|
|
.ep_mux_table = { 5, 9, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_AUDIO_DIVPMC, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "spdiftx_gclk",
|
|
.id = 85,
|
|
.r = { .max = 25000000 },
|
|
.ep = { "syspll_divpmcck", "audiopll_divpmcck", },
|
|
.ep_mux_table = { 5, 9, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_AUDIO_DIVPMC, },
|
|
.ep_count = 2,
|
|
},
|
|
|
|
{
|
|
.n = "tcb0_ch0_gclk",
|
|
.id = 88,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
|
|
"audiopll_divpmcck", "ethpll_divpmcck", },
|
|
.ep_mux_table = { 5, 7, 8, 9, 10, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_IMG_DIV,
|
|
ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC,
|
|
ID_PLL_ETH_DIV, },
|
|
.ep_count = 5,
|
|
},
|
|
|
|
{
|
|
.n = "tcb1_ch0_gclk",
|
|
.id = 91,
|
|
.r = { .max = 200000000 },
|
|
.ep = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
|
|
"audiopll_divpmcck", "ethpll_divpmcck", },
|
|
.ep_mux_table = { 5, 7, 8, 9, 10, },
|
|
.ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_IMG_DIV,
|
|
ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC,
|
|
ID_PLL_ETH_DIV, },
|
|
.ep_count = 5,
|
|
},
|
|
};
|
|
|
|
/**
|
|
* Clock setup description
|
|
* @cid: clock id corresponding to clock subsystem
|
|
* @pid: parent clock id corresponding to clock subsystem
|
|
* @rate: clock rate
|
|
* @prate: parent rate
|
|
*/
|
|
static const struct pmc_clk_setup {
|
|
unsigned int cid;
|
|
unsigned int pid;
|
|
unsigned long rate;
|
|
unsigned long prate;
|
|
} sama7g5_clk_setup[] = {
|
|
{
|
|
.cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_ETH_FRAC),
|
|
.rate = 625000000,
|
|
},
|
|
|
|
{
|
|
.cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_ETH_DIV),
|
|
.rate = 625000000,
|
|
},
|
|
};
|
|
|
|
#define SAMA7G5_MAX_MUX_ALLOCS (64)
|
|
|
|
#define prepare_mux_table(_allocs, _index, _dst, _src, _num, _label) \
|
|
do { \
|
|
int _i; \
|
|
if ((_index) >= SAMA7G5_MAX_MUX_ALLOCS) { \
|
|
debug("%s(): AT91: MUX: insufficient space\n", \
|
|
__func__); \
|
|
goto _label; \
|
|
} \
|
|
(_dst) = kzalloc(sizeof(*(_dst)) * (_num), GFP_KERNEL); \
|
|
if (!(_dst)) \
|
|
goto _label; \
|
|
(_allocs)[(_index)++] = (_dst); \
|
|
for (_i = 0; _i < (_num); _i++) \
|
|
(_dst)[_i] = (_src)[_i]; \
|
|
} while (0)
|
|
|
|
static int sama7g5_clk_probe(struct udevice *dev)
|
|
{
|
|
void __iomem *base = (void *)devfdt_get_addr(dev);
|
|
unsigned int *clkmuxallocs[SAMA7G5_MAX_MUX_ALLOCS];
|
|
unsigned int *muxallocs[SAMA7G5_MAX_MUX_ALLOCS];
|
|
const char *p[10];
|
|
unsigned int cm[10], m[10], *tmpclkmux, *tmpmux;
|
|
struct clk clk, *c, *parent;
|
|
bool main_osc_bypass;
|
|
int ret, muxallocindex = 0, clkmuxallocindex = 0, i, j;
|
|
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
memset(muxallocs, 0, ARRAY_SIZE(muxallocs));
|
|
memset(clkmuxallocs, 0, ARRAY_SIZE(clkmuxallocs));
|
|
|
|
ret = clk_get_by_index(dev, 0, &clk);
|
|
if (ret)
|
|
return ret;
|
|
ret = clk_get_by_id(clk.id, &c);
|
|
if (ret)
|
|
return ret;
|
|
clk_names[ID_TD_SLCK] = kmemdup(clk_hw_get_name(c),
|
|
strlen(clk_hw_get_name(c)) + 1, GFP_KERNEL);
|
|
if (!clk_names[ID_TD_SLCK])
|
|
return -ENOMEM;
|
|
|
|
ret = clk_get_by_index(dev, 1, &clk);
|
|
if (ret)
|
|
return ret;
|
|
ret = clk_get_by_id(clk.id, &c);
|
|
if (ret)
|
|
return ret;
|
|
clk_names[ID_MD_SLCK] = kmemdup(clk_hw_get_name(c),
|
|
strlen(clk_hw_get_name(c)) + 1, GFP_KERNEL);
|
|
if (!clk_names[ID_MD_SLCK])
|
|
return -ENOMEM;
|
|
|
|
ret = clk_get_by_index(dev, 2, &clk);
|
|
if (ret)
|
|
return ret;
|
|
clk_names[ID_MAIN_XTAL] = kmemdup(clk_hw_get_name(&clk),
|
|
strlen(clk_hw_get_name(&clk)) + 1, GFP_KERNEL);
|
|
if (!clk_names[ID_MAIN_XTAL])
|
|
return -ENOMEM;
|
|
|
|
ret = clk_get_by_index(dev, 3, &clk);
|
|
if (ret)
|
|
goto fail;
|
|
clk_names[ID_MAIN_RC] = kmemdup(clk_hw_get_name(&clk),
|
|
strlen(clk_hw_get_name(&clk)) + 1, GFP_KERNEL);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
main_osc_bypass = dev_read_bool(dev, "atmel,main-osc-bypass");
|
|
|
|
/* Register main rc oscillator. */
|
|
clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_RC_OSC),
|
|
at91_clk_main_rc(base, clk_names[ID_MAIN_RC_OSC],
|
|
clk_names[ID_MAIN_RC]));
|
|
|
|
/* Register main oscillator. */
|
|
clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_OSC),
|
|
at91_clk_main_osc(base, clk_names[ID_MAIN_OSC],
|
|
clk_names[ID_MAIN_XTAL], main_osc_bypass));
|
|
|
|
/* Register mainck. */
|
|
p[0] = clk_names[ID_MAIN_RC_OSC];
|
|
p[1] = clk_names[ID_MAIN_OSC];
|
|
cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_RC_OSC);
|
|
cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_OSC);
|
|
prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 2,
|
|
fail);
|
|
clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK),
|
|
at91_clk_sam9x5_main(base, clk_names[ID_MAINCK], p,
|
|
2, tmpclkmux, PMC_TYPE_CORE));
|
|
|
|
/* Register PLL fracs clocks. */
|
|
for (i = 0; i < ARRAY_SIZE(sama7g5_plls); i++) {
|
|
if (sama7g5_plls[i].t != PLL_TYPE_FRAC)
|
|
continue;
|
|
|
|
clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sama7g5_plls[i].cid),
|
|
sam9x60_clk_register_frac_pll(base, sama7g5_plls[i].n,
|
|
sama7g5_plls[i].p, sama7g5_plls[i].id,
|
|
&pll_characteristics, sama7g5_plls[i].l,
|
|
sama7g5_plls[i].c));
|
|
}
|
|
|
|
/* Register PLL div clocks. */
|
|
for (i = 0; i < ARRAY_SIZE(sama7g5_plls); i++) {
|
|
if (sama7g5_plls[i].t != PLL_TYPE_DIV)
|
|
continue;
|
|
|
|
clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sama7g5_plls[i].cid),
|
|
sam9x60_clk_register_div_pll(base, sama7g5_plls[i].n,
|
|
sama7g5_plls[i].p, sama7g5_plls[i].id,
|
|
&pll_characteristics, sama7g5_plls[i].l,
|
|
sama7g5_plls[i].c));
|
|
}
|
|
|
|
/* Register MCK0_PRES clock. */
|
|
p[0] = clk_names[ID_MD_SLCK];
|
|
p[1] = clk_names[ID_MAINCK];
|
|
p[2] = clk_names[ID_PLL_CPU_DIV];
|
|
p[3] = clk_names[ID_PLL_SYS_DIV];
|
|
cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
|
|
cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
|
|
cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_CPU_DIV);
|
|
cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_SYS_DIV);
|
|
prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 2,
|
|
fail);
|
|
clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_PRES),
|
|
at91_clk_register_master_pres(base, clk_names[ID_MCK0_PRES], p,
|
|
4, &mck0_layout, &mck0_characteristics, tmpclkmux));
|
|
|
|
clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV),
|
|
at91_clk_register_master_div(base, clk_names[ID_MCK0_DIV],
|
|
clk_names[ID_MCK0_PRES], &mck0_layout, &mck0_characteristics));
|
|
|
|
/* Register MCK1-4 clocks. */
|
|
p[0] = clk_names[ID_MD_SLCK];
|
|
p[1] = clk_names[ID_TD_SLCK];
|
|
p[2] = clk_names[ID_MAINCK];
|
|
p[3] = clk_names[ID_MCK0_DIV];
|
|
m[0] = 0;
|
|
m[1] = 1;
|
|
m[2] = 2;
|
|
m[3] = 3;
|
|
cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
|
|
cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
|
|
cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
|
|
cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV);
|
|
for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) {
|
|
for (j = 0; j < sama7g5_mckx[i].ep_count; j++) {
|
|
p[4 + j] = sama7g5_mckx[i].ep[j];
|
|
m[4 + j] = sama7g5_mckx[i].ep_mux_table[j];
|
|
cm[4 + j] = AT91_TO_CLK_ID(PMC_TYPE_CORE,
|
|
sama7g5_mckx[i].ep_clk_mux_table[j]);
|
|
}
|
|
|
|
prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm,
|
|
4 + sama7g5_mckx[i].ep_count, fail);
|
|
prepare_mux_table(muxallocs, muxallocindex, tmpmux, m,
|
|
4 + sama7g5_mckx[i].ep_count, fail);
|
|
|
|
clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sama7g5_mckx[i].cid),
|
|
at91_clk_sama7g5_register_master(base,
|
|
sama7g5_mckx[i].n, p, 4 + sama7g5_mckx[i].ep_count,
|
|
tmpmux, tmpclkmux, sama7g5_mckx[i].c,
|
|
sama7g5_mckx[i].id));
|
|
}
|
|
|
|
/* Register UTMI clock. */
|
|
clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_UTMI),
|
|
at91_clk_sama7g5_register_utmi(base, "utmick",
|
|
clk_names[ID_MAIN_XTAL]));
|
|
|
|
/* Register programmable clocks. */
|
|
p[0] = clk_names[ID_MD_SLCK];
|
|
p[1] = clk_names[ID_TD_SLCK];
|
|
p[2] = clk_names[ID_MAINCK];
|
|
p[3] = clk_names[ID_MCK0_DIV];
|
|
p[4] = clk_names[ID_PLL_SYS_DIV];
|
|
p[5] = clk_names[ID_PLL_DDR_DIV];
|
|
p[6] = clk_names[ID_PLL_IMG_DIV];
|
|
p[7] = clk_names[ID_PLL_BAUD_DIV];
|
|
p[8] = clk_names[ID_PLL_AUDIO_DIVPMC];
|
|
p[9] = clk_names[ID_PLL_ETH_DIV];
|
|
cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
|
|
cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
|
|
cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
|
|
cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV);
|
|
cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_SYS_DIV);
|
|
cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_DDR_DIV);
|
|
cm[6] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_IMG_DIV);
|
|
cm[7] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_BAUD_DIV);
|
|
cm[8] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_AUDIO_DIVPMC);
|
|
cm[9] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_ETH_DIV);
|
|
for (i = 0; i < ARRAY_SIZE(sama7g5_prog); i++) {
|
|
prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm,
|
|
10, fail);
|
|
|
|
clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sama7g5_prog[i].cid),
|
|
at91_clk_register_programmable(base, sama7g5_prog[i].n,
|
|
p, 10, i, &programmable_layout, tmpclkmux,
|
|
sama7g5_prog_mux_table));
|
|
}
|
|
|
|
/* System clocks. */
|
|
for (i = 0; i < ARRAY_SIZE(sama7g5_systemck); i++) {
|
|
clk_dm(AT91_TO_CLK_ID(PMC_TYPE_SYSTEM, sama7g5_systemck[i].cid),
|
|
at91_clk_register_system(base, sama7g5_systemck[i].n,
|
|
sama7g5_systemck[i].p, sama7g5_systemck[i].id));
|
|
}
|
|
|
|
/* Peripheral clocks. */
|
|
for (i = 0; i < ARRAY_SIZE(sama7g5_periphck); i++) {
|
|
clk_dm(AT91_TO_CLK_ID(PMC_TYPE_PERIPHERAL,
|
|
sama7g5_periphck[i].id),
|
|
at91_clk_register_sam9x5_peripheral(base,
|
|
&sama7g5_pcr_layout, sama7g5_periphck[i].n,
|
|
sama7g5_periphck[i].p, sama7g5_periphck[i].id,
|
|
&sama7g5_periphck[i].r));
|
|
}
|
|
|
|
/* Generic clocks. */
|
|
p[0] = clk_names[ID_MD_SLCK];
|
|
p[1] = clk_names[ID_TD_SLCK];
|
|
p[2] = clk_names[ID_MAINCK];
|
|
p[3] = clk_names[ID_MCK0_DIV];
|
|
m[0] = 0;
|
|
m[1] = 1;
|
|
m[2] = 2;
|
|
m[3] = 3;
|
|
cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
|
|
cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
|
|
cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
|
|
cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV);
|
|
for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) {
|
|
for (j = 0; j < sama7g5_gck[i].ep_count; j++) {
|
|
p[4 + j] = sama7g5_gck[i].ep[j];
|
|
m[4 + j] = sama7g5_gck[i].ep_mux_table[j];
|
|
cm[4 + j] = AT91_TO_CLK_ID(PMC_TYPE_CORE,
|
|
sama7g5_gck[i].ep_clk_mux_table[j]);
|
|
}
|
|
|
|
prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm,
|
|
4 + sama7g5_gck[i].ep_count, fail);
|
|
prepare_mux_table(muxallocs, muxallocindex, tmpmux, m,
|
|
4 + sama7g5_gck[i].ep_count, fail);
|
|
|
|
clk_dm(AT91_TO_CLK_ID(PMC_TYPE_GCK, sama7g5_gck[i].id),
|
|
at91_clk_register_generic(base, &sama7g5_pcr_layout,
|
|
sama7g5_gck[i].n, p, tmpclkmux, tmpmux,
|
|
4 + sama7g5_gck[i].ep_count, sama7g5_gck[i].id,
|
|
&sama7g5_gck[i].r));
|
|
}
|
|
|
|
/* Setup clocks. */
|
|
for (i = 0; i < ARRAY_SIZE(sama7g5_clk_setup); i++) {
|
|
ret = clk_get_by_id(sama7g5_clk_setup[i].cid, &c);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
if (sama7g5_clk_setup[i].pid) {
|
|
ret = clk_get_by_id(sama7g5_clk_setup[i].pid, &parent);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
ret = clk_set_parent(c, parent);
|
|
if (ret)
|
|
goto fail;
|
|
|
|
if (sama7g5_clk_setup[i].prate) {
|
|
ret = clk_set_rate(parent,
|
|
sama7g5_clk_setup[i].prate);
|
|
if (ret < 0)
|
|
goto fail;
|
|
}
|
|
}
|
|
|
|
if (sama7g5_clk_setup[i].rate) {
|
|
ret = clk_set_rate(c, sama7g5_clk_setup[i].rate);
|
|
if (ret < 0)
|
|
goto fail;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
for (i = 0; i < ARRAY_SIZE(muxallocs); i++)
|
|
kfree(muxallocs[i]);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(clkmuxallocs); i++)
|
|
kfree(clkmuxallocs[i]);
|
|
|
|
return -ENOMEM;
|
|
}
|
|
|
|
static const struct udevice_id sama7g5_clk_ids[] = {
|
|
{ .compatible = "microchip,sama7g5-pmc" },
|
|
{ /* Sentinel. */ },
|
|
};
|
|
|
|
U_BOOT_DRIVER(at91_sama7g5_pmc) = {
|
|
.name = "at91-sama7g5-pmc",
|
|
.id = UCLASS_CLK,
|
|
.of_match = sama7g5_clk_ids,
|
|
.ops = &at91_clk_ops,
|
|
.probe = sama7g5_clk_probe,
|
|
.flags = DM_FLAG_PRE_RELOC,
|
|
};
|