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c05be59ca8
Split master clock in 2 controlling block: one for prescaler one for
divider. This will allow referencing correctly the CPU clock and
master clock in device trees.
Reported-by: Eugen Hristev <eugen.hristev@microchip.com>
Fixes: a64862284f
("clk: at91: sam9x60: add support compatible with
CCF")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
397 lines
9.7 KiB
C
397 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Master clock support for AT91 architectures.
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*
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* Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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*
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* Based on drivers/clk/at91/clk-master.c from Linux.
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*/
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#include <asm/processor.h>
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#include <clk-uclass.h>
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#include <common.h>
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#include <div64.h>
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#include <dm.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/at91_pmc.h>
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#include "pmc.h"
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#define UBOOT_DM_CLK_AT91_MASTER_PRES "at91-master-clk-pres"
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#define UBOOT_DM_CLK_AT91_MASTER_DIV "at91-master-clk-div"
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#define UBOOT_DM_CLK_AT91_SAMA7G5_MASTER "at91-sama7g5-master-clk"
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#define MASTER_PRES_MASK 0x7
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#define MASTER_PRES_MAX MASTER_PRES_MASK
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#define MASTER_DIV_SHIFT 8
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#define MASTER_DIV_MASK 0x7
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#define PMC_MCR 0x30
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#define PMC_MCR_ID_MSK GENMASK(3, 0)
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#define PMC_MCR_CMD BIT(7)
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#define PMC_MCR_DIV GENMASK(10, 8)
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#define PMC_MCR_CSS GENMASK(20, 16)
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#define PMC_MCR_CSS_SHIFT (16)
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#define PMC_MCR_EN BIT(28)
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#define PMC_MCR_ID(x) ((x) & PMC_MCR_ID_MSK)
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#define MASTER_MAX_ID 4
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struct clk_master {
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void __iomem *base;
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const struct clk_master_layout *layout;
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const struct clk_master_characteristics *characteristics;
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const u32 *mux_table;
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const u32 *clk_mux_table;
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u32 num_parents;
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struct clk clk;
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u8 id;
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};
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#define to_clk_master(_clk) container_of(_clk, struct clk_master, clk)
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static inline bool clk_master_ready(struct clk_master *master)
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{
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unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY;
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unsigned int status;
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pmc_read(master->base, AT91_PMC_SR, &status);
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return !!(status & bit);
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}
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static int clk_master_enable(struct clk *clk)
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{
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struct clk_master *master = to_clk_master(clk);
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while (!clk_master_ready(master)) {
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debug("waiting for mck %d\n", master->id);
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cpu_relax();
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}
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return 0;
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}
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static ulong clk_master_pres_get_rate(struct clk *clk)
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{
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struct clk_master *master = to_clk_master(clk);
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const struct clk_master_layout *layout = master->layout;
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const struct clk_master_characteristics *characteristics =
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master->characteristics;
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ulong rate = clk_get_parent_rate(clk);
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unsigned int mckr;
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u8 pres;
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if (!rate)
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return 0;
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pmc_read(master->base, master->layout->offset, &mckr);
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mckr &= layout->mask;
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pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK;
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if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX)
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pres = 3;
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else
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pres = (1 << pres);
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return DIV_ROUND_CLOSEST_ULL(rate, pres);
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}
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static const struct clk_ops master_pres_ops = {
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.enable = clk_master_enable,
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.get_rate = clk_master_pres_get_rate,
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};
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struct clk *at91_clk_register_master_pres(void __iomem *base,
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const char *name, const char * const *parent_names,
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int num_parents, const struct clk_master_layout *layout,
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const struct clk_master_characteristics *characteristics,
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const u32 *mux_table)
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{
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struct clk_master *master;
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struct clk *clk;
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unsigned int val;
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int ret;
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if (!base || !name || !num_parents || !parent_names ||
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!layout || !characteristics || !mux_table)
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return ERR_PTR(-EINVAL);
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master = kzalloc(sizeof(*master), GFP_KERNEL);
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if (!master)
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return ERR_PTR(-ENOMEM);
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master->layout = layout;
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master->characteristics = characteristics;
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master->base = base;
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master->num_parents = num_parents;
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master->mux_table = mux_table;
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pmc_read(master->base, master->layout->offset, &val);
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clk = &master->clk;
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clk->flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL;
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ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER_PRES, name,
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parent_names[val & AT91_PMC_CSS]);
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if (ret) {
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kfree(master);
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clk = ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(at91_master_pres_clk) = {
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.name = UBOOT_DM_CLK_AT91_MASTER_PRES,
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.id = UCLASS_CLK,
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.ops = &master_pres_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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static ulong clk_master_div_get_rate(struct clk *clk)
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{
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struct clk_master *master = to_clk_master(clk);
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const struct clk_master_layout *layout = master->layout;
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const struct clk_master_characteristics *characteristics =
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master->characteristics;
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ulong rate = clk_get_parent_rate(clk);
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unsigned int mckr;
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u8 div;
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if (!rate)
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return 0;
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pmc_read(master->base, master->layout->offset, &mckr);
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mckr &= layout->mask;
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div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
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rate = DIV_ROUND_CLOSEST_ULL(rate, characteristics->divisors[div]);
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if (rate < characteristics->output.min)
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pr_warn("master clk is underclocked");
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else if (rate > characteristics->output.max)
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pr_warn("master clk is overclocked");
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return rate;
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}
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static const struct clk_ops master_div_ops = {
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.enable = clk_master_enable,
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.get_rate = clk_master_div_get_rate,
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};
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struct clk *at91_clk_register_master_div(void __iomem *base,
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const char *name, const char *parent_name,
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const struct clk_master_layout *layout,
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const struct clk_master_characteristics *characteristics)
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{
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struct clk_master *master;
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struct clk *clk;
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int ret;
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if (!base || !name || !parent_name || !layout || !characteristics)
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return ERR_PTR(-EINVAL);
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master = kzalloc(sizeof(*master), GFP_KERNEL);
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if (!master)
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return ERR_PTR(-ENOMEM);
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master->layout = layout;
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master->characteristics = characteristics;
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master->base = base;
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master->num_parents = 1;
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clk = &master->clk;
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clk->flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL;
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ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER_DIV, name,
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parent_name);
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if (ret) {
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kfree(master);
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clk = ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(at91_master_div_clk) = {
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.name = UBOOT_DM_CLK_AT91_MASTER_DIV,
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.id = UCLASS_CLK,
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.ops = &master_div_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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static int clk_sama7g5_master_set_parent(struct clk *clk, struct clk *parent)
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{
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struct clk_master *master = to_clk_master(clk);
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int index;
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index = at91_clk_mux_val_to_index(master->clk_mux_table,
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master->num_parents, parent->id);
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if (index < 0)
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return index;
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index = at91_clk_mux_index_to_val(master->mux_table,
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master->num_parents, index);
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if (index < 0)
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return index;
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pmc_write(master->base, PMC_MCR, PMC_MCR_ID(master->id));
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pmc_update_bits(master->base, PMC_MCR,
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PMC_MCR_CSS | PMC_MCR_CMD | PMC_MCR_ID_MSK,
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(index << PMC_MCR_CSS_SHIFT) | PMC_MCR_CMD |
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PMC_MCR_ID(master->id));
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return 0;
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}
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static int clk_sama7g5_master_enable(struct clk *clk)
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{
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struct clk_master *master = to_clk_master(clk);
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pmc_write(master->base, PMC_MCR, PMC_MCR_ID(master->id));
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pmc_update_bits(master->base, PMC_MCR,
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PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID_MSK,
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PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID(master->id));
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return 0;
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}
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static int clk_sama7g5_master_disable(struct clk *clk)
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{
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struct clk_master *master = to_clk_master(clk);
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pmc_write(master->base, PMC_MCR, master->id);
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pmc_update_bits(master->base, PMC_MCR,
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PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID_MSK,
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PMC_MCR_CMD | PMC_MCR_ID(master->id));
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return 0;
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}
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static ulong clk_sama7g5_master_set_rate(struct clk *clk, ulong rate)
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{
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struct clk_master *master = to_clk_master(clk);
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ulong parent_rate = clk_get_parent_rate(clk);
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ulong div, rrate;
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if (!parent_rate)
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return 0;
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div = DIV_ROUND_CLOSEST(parent_rate, rate);
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if ((div > (1 << (MASTER_PRES_MAX - 1))) || (div & (div - 1))) {
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return 0;
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} else if (div == 3) {
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rrate = DIV_ROUND_CLOSEST(parent_rate, MASTER_PRES_MAX);
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div = MASTER_PRES_MAX;
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} else {
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rrate = DIV_ROUND_CLOSEST(parent_rate, div);
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div = ffs(div) - 1;
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}
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pmc_write(master->base, PMC_MCR, master->id);
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pmc_update_bits(master->base, PMC_MCR,
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PMC_MCR_DIV | PMC_MCR_CMD | PMC_MCR_ID_MSK,
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(div << MASTER_DIV_SHIFT) | PMC_MCR_CMD |
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PMC_MCR_ID(master->id));
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return rrate;
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}
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static ulong clk_sama7g5_master_get_rate(struct clk *clk)
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{
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struct clk_master *master = to_clk_master(clk);
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ulong parent_rate = clk_get_parent_rate(clk);
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unsigned int val;
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ulong div;
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if (!parent_rate)
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return 0;
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pmc_write(master->base, PMC_MCR, master->id);
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pmc_read(master->base, PMC_MCR, &val);
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div = (val >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
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if (div == MASTER_PRES_MAX)
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div = 3;
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else
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div = 1 << div;
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return DIV_ROUND_CLOSEST(parent_rate, div);
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}
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static const struct clk_ops sama7g5_master_ops = {
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.enable = clk_sama7g5_master_enable,
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.disable = clk_sama7g5_master_disable,
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.set_rate = clk_sama7g5_master_set_rate,
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.get_rate = clk_sama7g5_master_get_rate,
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.set_parent = clk_sama7g5_master_set_parent,
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};
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struct clk *at91_clk_sama7g5_register_master(void __iomem *base,
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const char *name, const char * const *parent_names,
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int num_parents, const u32 *mux_table, const u32 *clk_mux_table,
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bool critical, u8 id)
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{
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struct clk_master *master;
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struct clk *clk;
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u32 val, index;
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int ret;
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if (!base || !name || !num_parents || !parent_names ||
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!mux_table || !clk_mux_table || id > MASTER_MAX_ID)
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return ERR_PTR(-EINVAL);
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master = kzalloc(sizeof(*master), GFP_KERNEL);
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if (!master)
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return ERR_PTR(-ENOMEM);
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master->base = base;
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master->id = id;
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master->mux_table = mux_table;
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master->clk_mux_table = clk_mux_table;
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master->num_parents = num_parents;
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pmc_write(master->base, PMC_MCR, master->id);
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pmc_read(master->base, PMC_MCR, &val);
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index = at91_clk_mux_val_to_index(master->mux_table,
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master->num_parents,
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(val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT);
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if (index < 0) {
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kfree(master);
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return ERR_PTR(index);
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}
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clk = &master->clk;
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clk->flags = CLK_GET_RATE_NOCACHE | (critical ? CLK_IS_CRITICAL : 0);
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ret = clk_register(clk, UBOOT_DM_CLK_AT91_SAMA7G5_MASTER, name,
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parent_names[index]);
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if (ret) {
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kfree(master);
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clk = ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(at91_sama7g5_master_clk) = {
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.name = UBOOT_DM_CLK_AT91_SAMA7G5_MASTER,
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.id = UCLASS_CLK,
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.ops = &sama7g5_master_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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const struct clk_master_layout at91rm9200_master_layout = {
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.mask = 0x31F,
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.pres_shift = 2,
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.offset = AT91_PMC_MCKR,
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};
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const struct clk_master_layout at91sam9x5_master_layout = {
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.mask = 0x373,
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.pres_shift = 4,
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.offset = AT91_PMC_MCKR,
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};
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